Article ID: 000086638 Content Type: Product Information & Documentation Last Reviewed: 04/18/2023

How long should I wait after nSTATUS goes high before sampling the AVST_READY signal when configuring Intel® Stratix® 10 devices in Avalon-ST configuration mode?

Environment

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Description

The AVST_READY signal doesn’t change to a valid value until after the nSTATUS pin goes high in Intel® Stratix® 10 devices when configuring in Avalon-ST mode. 

 

 

Resolution

It is recommended to wait for at least 500 us after the nSTATUS pin goes high before sampling AVST_READY and proceeding with the configuration process. 

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs