Article ID: 000086663 Content Type: Error Messages Last Reviewed: 03/13/2023

Error (175005): Could not find a location with: GPIO_SHARED_NOE0 of (locations affected)

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    This error may be seen in Intel® Quartus® Prime Pro Edition Software during compilation of all Intel Agilex® device targeted design that contains the Generic Serial Flash Interface Intel® FPGA IP design with exported conduits. This is because there is an Output Enable (OE) conflict in the design pin placement. The error may be duplicated on different pins assignments if there are multiple OE conflicts being detected.

    In all Intel Agilex devices, there is a pin placement requirement due to the fact that the OE hardware is shared amongst x4 DQ group pins. Thus, if there are two conduits having their own respective OE signals, they should be assigned to different x4 DQ group pins to avoid OE conflicts.

     

     

    Generic Serial Flash Interface Intel FPGA IP (viewed in Technology Map Viewer)

     

    OE signalsExported Conduits
    dedicated_interface:data_buf[0]~0qspi_pins_data[0]
    dedicated_interface:data_buf[1]~1qspi_pins_data[1]
    dedicated_interface:data_buf[2]~2qspi_pins_data[2]
    qspi_pins_data[3]
    qspi_inf_inst:oe_regqspi_pins_dclk
    qspi_pins_ncs
    Resolution

    To avoid this error, exported conduits with different OE signals should be established in a different x4 DQ group, whereas exported conduits with a shared OE signal are recommended to be established within the same x4 DQ group. Example using an Intel Agilex®  device (AGFB027) is shown in the following table:

     

    Exported ConduitsPin Placementx4 DQ group (AGFB027)
    qspi_pins_data[0]W34DQ133
    qspi_pins_data[1]J35DQ135
    qspi_pins_data[2]
    qspi_pins_data[3]
    L38
    W38
    DQ132
    qspi_pins_dclk
    qspi_pins_ncs
    J39
    C38
    DQ134

     

    The information is available in Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide and Pin-Out Files for Intel FPGA.

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