Article ID: 000086767 Content Type: Troubleshooting Last Reviewed: 08/12/2021

Why do the EMIF Traffic Generator 2.0 idle cycle count and loop idle counter have a mismatch?

Environment

  • Intel® Quartus® Prime Pro Edition
  • External Memory Interfaces Intel® Stratix® 10 FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® Prime Pro Edition software version 20.4 and earlier, the number of idle cycles between successive loops in the EMIF Traffic Generator 2.0 (TG2) does not equal the loop idle counter when the number of reads or writes is 1. This problem only occurs when the number of loops is greater than 2 as reloading the loop idle counter is done incorrectly. The number of idle cycles between loops is one less than the loop idle counter.

    Resolution

    This problem is fixed starting in the Intel® Quartus® Prime Pro Edition software version 21.1.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs