Instructor-Led Training: Intel® FPGA Timing Closure: Lecture

Description

One of the greatest and most frustrating FPGA design challenges is closing timing. It is very common to find, after performing a complete timing analysis on an FPGA design, that one or more timing reports indicate a timing failure. How can this be corrected? The answer is not always obvious. This class teaches the techniques used by design specialists to close timing on designs that “push the envelope” of performance. Example techniques include thoroughly analyzing the design for common timing failures, adjusting settings and assignments according to tool recommendations, selecting the correct clock resources, and adjusting HDL code for optimal performance. This class is lecture only. There is a follow on workshop class that is lab based.