Instructor-Led Training: Altera® FPGA Timing Analysis: Hands-on Labs

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Intel® FPGA Development Tools Support Intel® FPGA Training Catalog

726460
2023-07-14
Public

Description

In this class, you will work hands-on labs on a virtual machine to practice your timing analysis skills. Come as you are to the class, no setup is needed. Prior knowledge of timing analysis concepts is required. If you need to learn those, before coming to class, attend the Timing Analysis: Lecture class. There will be a brief review of the SDC constraints starting the labs.

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You will learn how to constrain & analyze a design for timing using the Timing Analyzer in the Quartus® Prime Pro software v. 22.1. This includes writing Synopsys* Design Constraint (SDC) files, generating various timing reports in the Timing Analyzer & applying this knowledge to an FPGA design. Besides learning the basic requirements to ensure that your design meets timing, you will see how the Timing Analyzer makes it easy to create timing constraints to help you meet those requirements. Note: While the focus of this course is the Quartus Prime Pro software, much of the flow and constraints are valid with the Standard and Lite versions of the software.
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