H-Tile Hard IP Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683430
Date 5/03/2024
Public
Document Table of Contents

6.8.1. Disabling Background Calibration

H-Tile Hard IP for Ethernet IP core implements the Auto Adaptation triggering for RX PMA CTLE/DFE mode.

For Stratix® 10 H-tile production devices, disable the background calibration first prior to accessing the transceiver core reconfiguration register. The Stratix® 10 H-tile ES devices do not have background calibration.

In Quartus® Prime software version 19.2 onwards, use the following steps to access the transceiver core reconfiguration registers:

  1. Write 0x0 into register 0x542[0] of the transceiver control and status registers using the transceiver reconfiguration Avalon® -MM interface to disable background calibration.
  2. Access the transceiver register, for example, to perform the transceiver reconfiguration.
  3. Once completed, write 0x1 into register 0x542[0] of the transceiver control and status registers using the transceiver reconfiguration Avalon® -MM interface to enable background calibration.