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What is Static Update Partial Reconfiguration?
1.1. Tutorial Requirements
1.2. Reference Design Overview
1.3. Static Update Region Overview
1.4. Download Reference Design Files
1.5. Reference Design Walkthrough
1.6. Document Revision History of AN 987: Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
1.5.1. Step 1: Getting Started
1.5.2. Step 2: Create Design Partitions
1.5.3. Step 3: Allocate Placement and Routing Regions
1.5.4. Step 4: Define Personas
1.5.5. Step 5: Create Revisions
1.5.6. Step 6: Compile the Base Revision
1.5.7. Step 7: Set Up PR Implementation Revisions
1.5.8. Step 8: Change the SUPR Logic
1.5.9. Step 9: Program the Board
1.5.10. Modifying the SUPR Partition
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1. Static Update Partial Reconfiguration Tutorial for Intel Agilex® 7 FPGA Development Board
This application note demonstrates static update partial reconfiguration (SUPR) on the Intel Agilex® 7 F-Series or M-Series FPGA Development Board.
Partial reconfiguration (PR) allows you to reconfigure a portion of an Intel® FPGA dynamically, while the remaining FPGA continues to operate. PR implements multiple personas in a particular region in your design, without impacting operation in areas outside this region. This methodology provides the following advantages in systems in which multiple functions time-share the same FPGA resources:
- Allows run-time reconfiguration
- Increases design scalability
- Reduces system down-time
- Supports dynamic time-multiplexing functions in the design
- Lowers cost and power consumption by efficient use of board space
What is Static Update Partial Reconfiguration?
In traditional PR, any change to the static region requires recompilation of every persona. However, with SUPR you can define a specialized region that allows change, without requiring the recompilation of personas. This technique is useful for a portion of a design that you may possibly want to change for risk mitigation, but that never requires runtime reconfiguration.