Serial Digital Interface (SDI) II Intel® FPGA IP Release Notes

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Date 4/09/2024
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1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes
1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes x
1.1. SDI II Intel® FPGA IP v19.5.0 1.2. SDI II Intel® FPGA IP v19.4.0 1.3. SDI II Intel® FPGA IP v19.3.2 1.4. SDI II Intel® FPGA IP v19.3.0 1.5. SDI II Intel® FPGA IP v19.2.1 1.6. SDI II Intel® FPGA IP v19.2 1.7. SDI II Intel® FPGA IP v19.1 1.8. SDI II Intel® FPGA IP v18.1 Update 2 1.9. SDI II Intel® FPGA IP v18.1 Update 1 1.10. SDI II Intel® FPGA IP v18.1 1.11. SDI II Intel® FPGA IP v18.0 1.12. Intel FPGA SDI II IP Core v17.1 1.13. SDI II IP Core v17.0 1.14. SDI II IP Core v16.1 1.15. SDI II IP Core v16.0 1.16. SDI II IP Core v15.1 1.17. SDI II IP Core v15.0 1.18. SDI II IP Core v14.1 1.19. Serial Digital Interface (SDI) II User Guide Archives
1. Serial Digital Interface (SDI) II Intel FPGA IP Release Notes

1.10. SDI II Intel® FPGA IP v18.1

Table 9.  v18.1 September 2018
Description Impact

Enabled payload ID insertion into chroma streams and 6G-SDI with 8 streams interleaved for the IP core.

These changes are optional. If you do not upgrade your IP core, it does not have these new features.

Enhanced TRS detection in 6G-SDI and 12G-SDI for better performance for the IP core.

Fixed payload ID insertion issues on 1080p50/60 on 3G Level A and SD 525i video formats in the Arria® 10, Cyclone® 10 GX, and Stratix® 10 design examples.

Improved robustness in the serial loopback design during standard switching in the Arria® 10, Cyclone® 10 GX, and Stratix® 10 design examples.
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