Visible to Intel only — GUID: xrd1502439273567
Ixiasoft
Visible to Intel only — GUID: xrd1502439273567
Ixiasoft
HPS JTAG Pins
HPS Pin Function | Pin Description and Connection Guidelines | Pin Type | Valid Assignments |
---|---|---|---|
JTAG_TCK | HPS JTAG test clock input pin. Connect this pin through a 1-kΩ – 10-kΩ pull-down resistor to GND. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. The option to access the HPS JTAG interface through the FPGA JTAG pins is available in the Intel® Quartus® Prime Pro Edition. For more details, refer to AN 802: Intel® Stratix® 10 SoC Device Design Guidelines. |
Input | HPS_IOB_9 |
JTAG_TMS | HPS JTAG test mode select input pin. Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. |
Input | HPS_IOB_10 |
JTAG_TDO | HPS JTAG test data output pin. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. |
Output | HPS_IOB_11 |
JTAG_TDI | HPS JTAG test data input pin. Connect this pin to a 1-kΩ – 10-kΩ pull-up resistor to the VCCIO_HPS supply. Do not drive voltage higher than the VCCIO_HPS supply. You can use the FPGA dedicated JTAG pins as an option to access the HPS JTAG. |
Input | HPS_IOB_12 |