Intel® Cyclone® 10 GX Device Errata and Design Guidelines

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ID 683031
Date 8/03/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Cyclone® 10 GX Device Errata 2. Document Revision History for Intel® Cyclone® 10 GX Device Errata and Design Guidelines
1. Intel® Cyclone® 10 GX Device Errata x
1.1. Automatic Lane Polarity Inversion for PCIe Hard IP 1.2. High VCCBAT Current when VCC is Powered Down 1.3. Failure on Row Y59 When Using the Error Detection Cyclic Redundancy Check (EDCRC) or Partial Reconfiguration (PR) 1.4. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation
1. Intel® Cyclone® 10 GX Device Errata
2. Document Revision History for Intel® Cyclone® 10 GX Device Errata and Design Guidelines

1.4. GPIO Output may not meet the On-Chip Series Termination (Rs OCT) without Calibration Resistance Tolerance Specification or Current Strength Expectation

Description

The GPIO pull-up impedance may not meet the on-chip series termination (Rs OCT) without calibration resistance tolerance specification mentioned in the Intel® Cyclone® 10 GX device datasheet. While using the current strength selection, the GPIO output buffer may not meet expected current strength at VOH voltage level when driving HIGH.

Workaround

Enable the on-chip series termination (Rs OCT) with calibration in your design.

Status

Affects: All Intel® Cyclone® 10 GX devices

Status: No planned fix.

Level Two Title