AN 804: Implementing Analog-to-Digital Converter Multi-Link Designs with Intel® Stratix® 10 JESD204B RX IP Core

ID 683032
Date 1/16/2020
Public
Document Table of Contents

Editing Design Example Top-Level HDL for Synchronized ADC- Intel® Stratix® 10 Multi-Link

The generated statement in the Verilog HDL file uses the LINK system parameter as an index variable to generate the requisite number of instances for the multi-link use case.
  1. Open the top-level HDL file (altera_jesd204_ed_RX.sv) in a text editor.
  2. Modify the LINK system parameter to reflect the number of links in your design.
  3. Insert the newly exported ports from the Platform Designer at the Platform Designer instantiation.
  4. Follow these steps to make the connections for the Platform Designer ports:
    1. For RX link reset, distribute the rx_link_rst_n[0] wire from the reset sequencer in Platform Designer to IP cores and transport layers of the second and subsequent links. One way to achieve this is to hard code the index in rx_link_rst_n[i] wire in the transport layer instantiations generation loop with rx_link_rst_n[0].
    2. For RX frame reset, distribute the rx_frame_rst_n[0] wire from the reset sequencer in Platform Designer to the transport layers and pattern checkers of the second and subsequent links. One way to achieve this is to hard code the index in rx_frame_rst_n[i] wire in the transport layer and pattern checker instantiations generation loop with rx_frame_rst_n[0].
    3. Create the following wires to handle PHY resets. Example is shown in Verilog HDL:
      1. wire [LINK*L-1:0] rx_analogreset;
      2. wire [LINK*L-1:0] rx_analogreset_stat;
      3. wire [LINK*L-1:0] rx_digitalreset;
      4. wire [LINK*L-1:0] rx_digitalreset_stat;
      5. wire [LINK*L-1:0] rx_cal_busy;
      6. wire [LINK*L-1:0] rx_is_lockedtodata;
    4. Distribute the PHY reset, calibration busy and CDR locked signals from Transceiver PHY Reset Controller equally to each IP core.
      Example: For IP core with two transceiver channels, the rx_analogreset[1:0] is distributed to the link 0 IP core and rx_analogreset[3:2] is distributed to the link 1 IP core.
    5. Create the following wires for the dev_lane_aligned signals. Example is shown in Verilog HDL:
      1. wire [LINK*L-1:0] dev_lane_aligned;
      2. wire alldev_lane_aligned;
    6. Connect the dev_lane_aligned port of each IP core to an AND gate. Distribute the output of the AND gate to alldev_lane_aligned port of each IP core.
    7. For combined SYNC_N, connect the dev_sync_n port of the IP core to an AND gate. Connect the output of the AND gate to sync_n_out.
      Example:
      assign sync_n_out = &rx_dev_sync_n;
    8. For non-combined SYNC_N, scale up the dimension of sync_n_out port to match with the number of links.
      Example:
      output wire [LINK-1:0] sync_n_out,
    9. Leave the following ports unconnected:
      • sof
      • somf

      Example :

      .altera_jesd204_subsystem_rx_altera_jesd204_rx1_sof_export
      (/*leave open*/),
    10. For the rest of the ports, increase the index wires from 0 to 1 and subsequent numbers for the subsequent links.
      Example: jesd204_rx_link_data[1] wire should be connected to link 1 IP core and transport layer.
  5. Because there is only one PHY reset controller, the rx_ready signal of the subsequent link must be wired to the rx_ready signal of link 0 so that the rx_ready_or_rx_csr_lane_powerdown signal is connected correctly.
    generate
    	for (i=1; i<LINK; i=i+1) begin: RX_READY
    		assign xcvr_rst_ctrl_rx_ready[i] = xcvr_rst_ctrl_rx_ready[0];
    	end
    endgenerate
    
  6. Save the top-level HDL file changes.