AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree socfpga-linux/arch/arm/boot/dts/socfpga_arria10.dtsi Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Critical Information in the Default Device Tree

Listed below is the critical information provided in the default device tree, which is located with the Linux kernel source. /soc/base_fpga_region defines an empty FPGA region that is filled in by loading a device tree overlay after boot. This entry links to the FPGA manager, which is used to configure this FPGA region. In the example in this document, you add a PR FPGA region as a child node of /soc/base_fpga_region . This region inherits the link to the FPGA manager created in this boot device tree.

socfpga-linux/arch/arm/boot/dts/socfpga_arria10.dtsi

/ {
	#address-cells = <1>;
	#size-cells = <1>;
        
        soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges;

		base_fpga_region {
			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;

			#address-cells = <0x1>;
			#size-cells = <0x1>;
			
			/*
			 * NOTE: This node will be the parent for
			 *       the PR FPGA Region that is managed
			 *       using device tree overlays. The child
			 *       FPGA Regions will inherit the link to
			 *       the FPGA Manger created here.
			 */
		};

		fpga_mgr: fpga-mgr@ffd03000 {
			compatible = "altr,socfpga-a10-fpga-mgr";
			reg = <0xffd03000 0x100
			       0xffcfe400 0x20>;
			clocks = <&l4_mp_clk>;
			resets = <&rst FPGAMGR_RESET>;
			reset-names = "fpgamgr";
		};

        };                
};
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