AN 791: Migrating the Avalon® Streaming Interface for PCI Express* to Intel® Stratix® 10 Devices

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ID 683036
Date 9/14/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Configuration Options 3. Interface and Signal Differences 4. Document Revision History for AN-791
3. Interface and Signal Differences x
3.1. Clock Interface 3.2. Avalon-ST TX Interface 3.3. Avalon-ST TX Credit Interface 3.4. Avalon-ST RX Interface 3.5. Status and Link Training Interface 3.6. Configuration Status Interface 3.7. Interrupt Interface 3.8. Error Interface 3.9. Reset 3.10. PHY Interface for PCI Express (PIPE) Interface 3.11. Test Interface
1. Introduction
2. Configuration Options
3. Interface and Signal Differences
4. Document Revision History for AN-791

3.1. Clock Interface

Table 2.  Clock Interface
Intel® Stratix® 10 Intel® Arria® 10, Stratix® V Comments

Not available

pld_clk

Intel® Stratix® 10:

There is no pld_clk input to the hard IP core. The hard IP drives a clock to the application. You must provide clock crossing logic if it is required.

Intel® Arria® 10 and Stratix® V: coreclkout_hip, the fixed frequency clock for the DLL and Transaction Layer (TL) can drive pld_clk. If a different clock source drives the application logic, it must be equal to or faster than coreclkout_hip.

Level Two Title