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Ixiasoft
Checking the Deterministic Latency
To check for deterministic latency, follow these steps:
- Restart the converter and reprogram the clocks and ADC.
- Restart and reconfigure the FPGA.
- Execute the .tcl code to initialize the JESD204B links.
- Read the RX Buffer Delay (RBD) count by typing the read_rx_status0 procedure in the Tcl Console and record the value. The RBD count is from the csr_rbd_count field in the rx_status0[10:3] register (at offset 0x80).
- Measure and record the number of link counts between the start of combined SYNC_N deassertion output from the two JESD204B IP cores to the first user data output, which is the assertion of the jesd204_rx_link_valid signal. Ensure the latency is constant for every converter and FPGA power cycle.
- Repeat step 1 to step 5 for a few times.
Example of the System Console output after executing the read_rx_status0 procedure:
% read_rx_status0
master_list_length = 1
RX Status0 (Link 0)= 0x00000009
RX Status0 (Link 1)= 0x00000009RX Status0 = 0x00000009 indicates the following conditions:
- bit[0]=1, JESD204B link is out of synchronization (SYNC_n deasserted).
- bit[3]=1, csr_rbd_count = 1
For detailed description of the csr_rbd_count field of the rx_status0[10:3] register (at offset 0x80), refer to the Addressmap Information for 'altera_jesd204_rx_regmap'.