Integer Arithmetic Intel® FPGA IP Cores Release Notes

ID 683061
Date 4/01/2024
Public

1.1.6. ALTERA_MULT_ADD IP Core v16.0

Table 7.  v16.0 May 2016
Description Impact
  • Added synchronous clear signal support.
  • Added What is the source for synchronous clear input? selection for the following registers in the GUI:
    • Output register of the adder unit
    • Register for addnsub1 input signal
    • Register for addnsub3 input signal
    • Register for dataa input signal
    • Register for datab input signal
    • Register for scainouta output signal
    • Register for datac input signal
    • Register for signa input signal
    • Register for signb input signal
    • Register for coefsel[0..3] input signals
    • Register for accum_sload and sload_accum input signals
    • Register for negate input signal
    • Second register for signa and signb input signals
    • Register for systolic delay input signals