AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

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ID 683092
Date 4/03/2019
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Document Table of Contents x
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs x
Introduction to MIPI D-PHY Overview on MIPI Operation Functional Description: FPGA Receiving Interface and FPGA Transmitting Interface I/O Standards for MIPI D-PHY Implementation MIPI D-PHY Specifications FPGA I/O Standard Specifications IBIS Simulation PCB Design Guidelines Conclusion Document Revision History for AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs
MIPI D-PHY Specifications x
MIPI D-PHY Specifications for Receiver MIPI D-PHY Specifications for Transmitter
FPGA I/O Standard Specifications x
FPGA I/O Standard Specifications for MIPI Receiver FPGA I/O Standard Specifications for MIPI Transmitter
IBIS Simulation x
FPGA As Receiver: HS-RX and LP-RX Modes Simulation FPGA As Receiver: Simulation Results FPGA As Transmitter: HS-TX and LP-TX Modes Simulation FPGA As Transmitter: Simulation Results
FPGA As Receiver: Simulation Results x
FPGA As Receiver: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Receiver: Simulation Results Using Cyclone® V Devices FPGA As Receiver: Simulation Results Using Intel® MAX® 10 Devices
FPGA As Transmitter: Simulation Results x
FPGA As Transmitter: Simulation Results Using Cyclone® IV and Intel® Cyclone® 10 LP Devices FPGA As Transmitter: Simulation Results Using Cyclone® V Devices FPGA As Transmitter: Simulation Results Using Intel® MAX® 10 Devices
AN 754: MIPI D-PHY Solution with Passive Resistor Networks in Intel® Low-Cost FPGAs

FPGA I/O Standard Specifications for MIPI Receiver

The DC specifications for 1.2 V LVCMOS, HSTL-12, and LVDS I/O standards are as stipulated in the device datasheets for the respective devices. When an FPGA functions as a MIPI D-PHY receiver, the transmitted high-speed and low-power signals from the MIPI D-PHY transmitter are expected to meet these FPGA I/O standards specifications with passive resistor network.

Table 6.  1.2 V LVCMOS I/O Standard DC Specifications
I/O Standard VCCIO (V) VIL (V) VIH (V)
Min Typ Max Min Max Min Max
1.2 V 1.14 1.2 1.26 –0.3 0.35 × VCCIO 0.65 × VCCIO VCCIO + 0.3
Table 7.  Single-Ended HSTL-12 I/O Reference Voltage Specifications
I/O Standard VCCIO (V) VREF (V) VTT (V)
Min Typ Max Min Typ Max Min Typ Max
HSTL-12 Class I, II 1.14 1.2 1.26 0.48 × VCCIO 6 0.50 × VCCIO 6 0.52 × VCCIO 6 — 0.50 × VCCIO —
0.47 × VCCIO 7 0.50 × VCCIO 7 0.53 × VCCIO 7
Table 8.  Single-Ended HSTL-12 I/O Standard Signal Specifications
I/O Standard VIL(DC) (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V)
Min Max Min Max Min Max Min Max
HSTL-12 Class I, II –0.15 VREF – 0.08 VREF + 0.08 VCCIO + 0.15 –0.24 VREF – 0.15 VREF + 0.15 VCCIO + 0.24
Table 9.  LVDS I/O Standard DC Specifications
I/O Standard VCCIO (V) VID (V) VICM (V)
Min Typ Max Min Max Min Condition Max
LVDS 2.375 2.5 2.625 100 — 0.05 DMAX ≤ 500 Mbps 1.8
0.55 500 Mbps ≤ DMAX ≤ 700 Mbps 1.8
1.05 DMAX > 700 Mbps 1.55
6 Value shown refers to DC input reference voltage, VREF(DC).
7 Value shown refers to AC input reference voltage, VREF(AC).
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