Erasure Decoder Reference Design

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ID 683099
Date 5/02/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the Erasure Decoder Reference Design 2. Erasure Decoder Functional Description 3. Erasure Decoder IP Core Parameters 4. Erasure Decoder Interfaces and Signals
4. Erasure Decoder Interfaces and Signals x
4.1. Avalon-ST Interfaces in DSP IP Cores 4.2. Erasure Decoder IP Core Signals
1. About the Erasure Decoder Reference Design
2. Erasure Decoder Functional Description
3. Erasure Decoder IP Core Parameters
4. Erasure Decoder Interfaces and Signals

4. Erasure Decoder Interfaces and Signals

The Avalon-ST interface supports backpressure, which is a flow control mechanism, where a sink can indicate to a source to stop sending data.

The ready latency on the Avalon-ST input interface is 0; the number of symbols per beat is fixed to 1.

The clock and reset interfaces drive or receive the clock and reset signal to synchronize the Avalon-ST interfaces.

Level Two Title