5G LDPC Intel® FPGA IP User Guide

ID 683107
Date 4/01/2024
Public
Document Table of Contents

1.1. 5G LDPC Intel® FPGA IP Features

The 5G LDPC IP offers the following features:

  • 3GPP 5G LDPC specification compliant
  • For the decoder:
    • Improved block error rate (BLER) performance
    • Improved power efficiency of IP
    • Per-block modifiable code block length, code rate, base graph, and maximum number of iterations
    • Configurable input precision
    • Layered decoder scheduling architecture to double the speed of convergence compared to non-layered architecture
    • Early termination based on syndrome check on each iteration
    • Single or dual decoders
  • For the encoder: per-block modifiable code block length and code rate
  • No external memory requirement
  • MATLAB and C++ models for performance simulation and RTL test vector generation
  • Verilog HDL testbench option
  • Avalon® streaming input and output interfaces