E-Tile JESD204C Intel® FPGA IP User Guide

Download PDF
ID 683108
Date 1/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the E-Tile JESD204C Intel FPGA IP User Guide 2. Overview of the JESD204C Intel FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the JESD204C Intel® FPGA IP 6. JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. E-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. JESD204C Intel® FPGA IP Features 2.4. Presets 2.5. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel® FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. JESD204C IP Component Files 4.5. Creating a New Intel® Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the JESD204C Intel® FPGA IP x
5.1. JESD204C TX and RX Reset Sequence 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Deterministic Latency
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter Registers 8.2. Receiver Registers
1. About the E-Tile JESD204C Intel FPGA IP User Guide
2. Overview of the JESD204C Intel FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the JESD204C Intel® FPGA IP
6. JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. E-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the E-Tile JESD204C Intel® FPGA IP User Guide

2.5. Performance and Resource Utilization

Table 9.   JESD204C Intel® FPGA IP Performance
Device Family PMA Speed Grade FPGA Fabric Speed Grade Enable Soft PCS (Gbps)
Intel Agilex® 7 (E-tile) 1 –1 5.0 to 28.9
2 –2 5.0 to 28.3
–3 5.0 to 25.6
3 –2 5.0 to 17.4
–3 5.0 to 17.4
Intel® Stratix® 10 (E-tile) 1 –1 5.0 to 28.9
–2 5.0 to 25.6
2 –1 5.0 to 28.3
–2 5.0 to 25.6
3 –1 5.0 to 17.4
–2 5.0 to 17.4
–3 5.0 to 17.4

The following table lists the estimated resource utilization data of the JESD204C IP. These results are obtained using the Intel® Quartus® Prime software targeting the Intel Agilex® 7, AGFB014R24A3E3VR0 device and Intel® Stratix® 10, 1ST280EY3F55E3VGS1 device.

The variations for resource utilization are configured with the following parameter settings:

Table 10.  Parameter Settings to Obtain the Resource Utilization Data
Parameter Setting
JESD204C Wrapper Base and PHY
JESD204C Subclass 1
Data Rate 17.4 Gbps
Bonding Mode Non-bonded
Reference Clock Frequency 263.636363 MHz
Enable Scrambler (SCR) On
Enable Error Code Correction (ECC_EN) Off
Table 11.   JESD204C IP Resource Utilization for Intel Agilex® 7 Devices
Variants L M F FCLK_MULP WIDTH_MULP ALM ALUT Logic Register M20K
TX 4 8 6 1 8 6885 6488 9113 2
4 8 6 2 4 7012 7080 9780 2
4 8 4 1 4 5382 5810 7509 2
4 8 4 2 2 6311 6876 9458 2
2 8 6 1 8 3901 3883 5306 2
2 8 6 2 4 4066 4247 5916 2
8 8 3 1 16 12492 11374 15988 2
8 8 3 2 8 12983 12577 18074 2
3 8 4 1 2 4410 4801 6290 2
3 8 4 2 1 5030 5617 7604 2
RX 2 8 12 1 4 5236 5780 6434 10
2 8 12 2 2 4755 5347 5846 10
1 2 8 1 4 2650 3189 3428 4
1 2 8 2 2 2637 3224 3436 4
1 4 24 1 4 3281 3881 4311 6
1 4 24 2 2 2963 3567 3919 6
8 1 1 1 16 13582 15237 14634 34
8 1 1 2 8 13743 16028 15894 34
3 2 4 1 4 5560 6244 6209 9
3 2 4 2 2 5717 6658 6741 12
Table 12.   JESD204C IP Resource Utilization for Intel® Stratix® 10 Devices
Variants L M F FCLK_MULP WIDTH_MULP ALM ALUT Logic Register M20K
TX 4 8 6 1 8 6865 6474 9253 2
4 8 6 2 4 7002 7084 10092 2
4 8 4 1 4 5398 5829 7708 2
4 8 4 2 2 6712 7445 10171 2
2 8 6 1 8 3944 3881 5369 2
2 8 6 2 4 4190 4310 6015 2
8 8 3 1 16 12601 11494 16877 2
8 8 3 2 8 13157 12746 18645 2
3 8 4 1 2 4405 4827 6344 2
3 8 4 2 1 5052 5638 7678 2
RX 2 8 12 1 4 5266 5827 6349 10
2 8 12 2 2 4819 5420 5944 10
1 2 8 1 4 2642 3204 3385 4
1 2 8 2 2 2672 3214 3484 4
1 4 24 1 4 3243 3837 4166 6
1 4 24 2 2 3027 3585 3914 6
8 1 1 1 16 13511 15225 14903 34
8 1 1 2 8 13344 15812 14891 34
3 2 4 1 4 5524 6228 6332 9
3 2 4 2 2 5751 6673 6966 12
Level Two Title