High-speed Reed-Solomon IP Core User Guide

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ID 683120
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the High-speed Reed-Solomon IP Core 2. High-speed Reed-Solomon IP Core Getting Started 3. High-speed Reed-Solomon IP Core Functional Description 4. High-speed Reed-Solomon IP Core User Guide Document Revision History A. High-Speed Reed-Solomon IP Core Document Archive
1. About the High-speed Reed-Solomon IP Core x
1.1. Reed-Solomon II versus High-Speed Reed Solomon Intel® FPGA IP 1.2. High-speed Reed-Solomon IP Core Features 1.3. High-Speed Reed-Solomon IP Device Family Support 1.4. DSP IP Core Verification 1.5. High-speed Reed-Solomon IP Core Release Information 1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization
2. High-speed Reed-Solomon IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. High-speed Reed-Solomon IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. High-speed Reed-Solomon IP Core Functional Description x
3.1. High-Speed Reed-Solomon Architecture 3.2. High-Speed Reed-Solomon IP Core Parameters 3.3. High-speed Reed-Solomon IP Core Interfaces and Signals
3.1. High-Speed Reed-Solomon Architecture x
3.1.1. High-Speed Reed-Solomon Encoder 3.1.2. High-Speed Reed-Solomon Decoder
3.3. High-speed Reed-Solomon IP Core Interfaces and Signals x
3.3.1. High-speed Reed-Solomon IP Core Signals
1. About the High-speed Reed-Solomon IP Core
2. High-speed Reed-Solomon IP Core Getting Started
3. High-speed Reed-Solomon IP Core Functional Description
4. High-speed Reed-Solomon IP Core User Guide Document Revision History
A. High-Speed Reed-Solomon IP Core Document Archive

3.1. High-Speed Reed-Solomon Architecture

The encoder receives data packets and generates the check symbols; the decoder detects and corrects errors.

The High-speed Reed-Solomon IP core has a parallelized architecture to achieve very high throughout. The inputs and outputs contain multiple data symbols.

The fracturable decoder has preset parameters to support 4 x 25 GbE, 2 x 50 GbE and 1 x 100 GbE with parallelism p of 8, 16, and 32, respectively.


Section Content
High-Speed Reed-Solomon Encoder
High-Speed Reed-Solomon Decoder

Level Two Title