High-speed Reed-Solomon IP Core User Guide

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ID 683120
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the High-speed Reed-Solomon IP Core 2. High-speed Reed-Solomon IP Core Getting Started 3. High-speed Reed-Solomon IP Core Functional Description 4. High-speed Reed-Solomon IP Core User Guide Document Revision History A. High-Speed Reed-Solomon IP Core Document Archive
1. About the High-speed Reed-Solomon IP Core x
1.1. Reed-Solomon II versus High-Speed Reed Solomon Intel® FPGA IP 1.2. High-speed Reed-Solomon IP Core Features 1.3. High-Speed Reed-Solomon IP Device Family Support 1.4. DSP IP Core Verification 1.5. High-speed Reed-Solomon IP Core Release Information 1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization
2. High-speed Reed-Solomon IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. High-speed Reed-Solomon IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. High-speed Reed-Solomon IP Core Functional Description x
3.1. High-Speed Reed-Solomon Architecture 3.2. High-Speed Reed-Solomon IP Core Parameters 3.3. High-speed Reed-Solomon IP Core Interfaces and Signals
3.1. High-Speed Reed-Solomon Architecture x
3.1.1. High-Speed Reed-Solomon Encoder 3.1.2. High-Speed Reed-Solomon Decoder
3.3. High-speed Reed-Solomon IP Core Interfaces and Signals x
3.3.1. High-speed Reed-Solomon IP Core Signals
1. About the High-speed Reed-Solomon IP Core
2. High-speed Reed-Solomon IP Core Getting Started
3. High-speed Reed-Solomon IP Core Functional Description
4. High-speed Reed-Solomon IP Core User Guide Document Revision History
A. High-Speed Reed-Solomon IP Core Document Archive

1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization

The parameters you chose affect the performacen and resource utilization.

Decoder

Table 4.  Performance and Resource Utilization for Arria 10 DevicesTypical expected performance using the Quartus Prime software with with Arria 10 (10AX115R4F40I3SG) devices for RS(n,k) where n is the codeword length and k the number of information symbols. The M20K numbers in brackets indicate the M20K usage when you turn on True-dual port ROM.
Parameters ALM Memory M20K fMAX (MHz)
RS Code Parallelism (P) Latency Favor ROM

(255,239)

15

 91 No 5092 3 351
Yes 4545 20 (12) 335
132 No 5160 3 444
Yes 4583 20 (12) 439

(528,514)

 32 87 No 15,127 8 412
Yes 8,418 44 (25) 361
115 No 15,053 8 429
Yes 8,467 44 (25) 431

(528,514)

 16 99 No 8282 4 377
Yes 4665 21 (13) 374
127 No 8225 4 429
Yes 4712 21 (13) 448

(528,514)

 8 132 No 5192 2 352
Yes 3313 11 (4) 375
160 No 5174 2 473
Yes 3273 11 (4) 461

(544,514)

 136 134 No 96,606 34 321
Yes 70257 185 (110) 317
194 No 95,982 34 340
Yes 70527 185 (110) 330

(544,514)

 34 151 No 28335 9 345
Yes 21058 45 (28) 330
211 No 28044 9 394
Yes 21018 45 (28) 380
Table 5.  Performance and Resource Utilization for Arria 10 Devices (Fracturable IP Core)Typical expected performance using the Quartus Prime software with with Arria 10 (10AX115R4F40I3SG) and (10AX115R2F40I1SG) devices for RS(n,k) where n is the codeword length and k the number of information symbols.
Parameters ALM Memory M20K fMAX (MHz)
RS Code Latency I1 I3
(528,514) 112 10,834 24 401 336
128 10,910 24 460 384
164 10,812 25 440 363
196 11,029 25 451 396
Table 6.  Performance and Resource Utilization for Stratix V DevicesTypical expected performance using the Quartus Prime software with Stratix V (5SGXEA7H3F35C3) devices for RS(n,k) where n is the codeword length and k the number of information symbols.. The M20K numbers in brackets indicate the M20K usage when you turn on True-dual port ROM.
Parameters ALM Memory M20K fMAX (MHz)
RS Code Parallelism (P) Latency Favor ROM

(255,239)

15

 91 No 4894 3 351
Yes 4426 20 335
123 No 5077 3 444
Yes 4354 20 439

(528,514)

 32 87 No 14,948 8 390
Yes 8,418 44 (25) 361
115 No 14,916 8 437
Yes 7,735 44 (25) 394

(528,514)

 16 99 No 8126 4 377
Yes 4493 21 (13) 374
127 No 8060 4 429
Yes 4523 21 (13) 448

(528,514)

 8 132 No 5174 2 352
Yes 3303 11 (4) 375
160 No 5191 2 473
Yes 3244 11 (4) 461

(544,514)

 32 146 No 27090 8 286
Yes 19801 44 280
206 No 26724 8 365
Yes 19463 44 357

Encoder

Table 7.  Performance and Resource Utilization for Arria 10 DevicesTypical expected performance using the Quartus Prime software with with Arria 10 (10AX115R4F40I3SG) devices.
Parameters ALM fMAX (MHz)
RS Code Parallelism (P)
(255,239) 15 1,500 541
(528,514) 132 12,346 327
33 4,003 430
16 2,666 484
8 2,104 498
(544,514) 136 25,750 309
32 9,824 381
Table 8.  Performance and Resource Utilization for Stratix V DevicesTypical expected performance using the Quartus Prime software with Stratix V (5SGXEA7H3F35C3) devices.
Parameters ALM fMAX (MHz)
RS Code Parallelism (P)
(255,239) 15 2,095 546
(528,514) 132 11677 307
33 3917 416
16 2633 473
8 2004 462
(544,514) 136 23819 306
32 9343 369
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