Advanced SEU Detection Intel® FPGA IP Release Notes

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Date 4/01/2024
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Advanced SEU Detection Intel® FPGA IP Release Notes
Advanced SEU Detection Intel® FPGA IP Release Notes x
Advanced SEU Detection Intel® FPGA IP (stratix10_asd) v19.4.0 Advanced SEU Detection Intel® FPGA IP (stratix10_asd) v19.3.1 Advanced SEU Detection Intel FPGA IP Core (altera_adv_seu_detection) v18.0 Advanced SEU Detection Intel® FPGA IP (stratix10_asd) v19.2.0 Intel FPGA Advanced SEU Detection IP Core (altera_adv_seu_detection) v17.1 Altera Advanced SEU Detection IP Core (altera_adv_seu_detection) v14.1
Advanced SEU Detection Intel® FPGA IP Release Notes

Altera Advanced SEU Detection IP Core (altera_adv_seu_detection) v14.1

Table 6.  v14.1 December 2014
Description Impact
Added support for double-adjacent SEU sensitivity processing. Initiates an .smh lookup for correctable double-adjacent EDCRC errors instead of identifying such SEU as critical.
Added critical_clear signal to errors interface -
Added busy signal to errors interface For on-chip processing configuration only.
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