Embedded Peripherals IP User Guide

ID 683130
Date 2/16/2024
Public

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Document Table of Contents
1. Introduction 2. Avalon® -ST Multi-Channel Shared Memory FIFO Core 3. Avalon® -ST Single-Clock and Dual-Clock FIFO Cores 4. Avalon® -ST Serial Peripheral Interface Core 5. SPI Core 6. SPI Agent/JTAG to Avalon® Host Bridge Cores 7. Intel eSPI Agent Core 8. eSPI to LPC Bridge Core 9. Ethernet MDIO Core 10. Intel FPGA 16550 Compatible UART Core 11. UART Core 12. JTAG UART Core 13. Intel FPGA Avalon® Mailbox Core 14. Intel FPGA Avalon® Mutex Core 15. Intel FPGA Avalon® I2C (Host) Core 16. Intel FPGA I2C Agent to Avalon® -MM Host Bridge Core 17. Intel FPGA Avalon® Compact Flash Core 18. EPCS/EPCQA Serial Flash Controller Core 19. Intel FPGA Serial Flash Controller Core 20. Intel FPGA Serial Flash Controller II Core 21. Intel FPGA Generic QUAD SPI Controller Core 22. Intel FPGA Generic QUAD SPI Controller II Core 23. Interval Timer Core 24. Intel FPGA Avalon FIFO Memory Core 25. On-Chip Memory (RAM and ROM) Intel FPGA IP 26. On-Chip Memory II (RAM or ROM) Intel FPGA IP 27. Optrex 16207 LCD Controller Core 28. PIO Core 29. PLL Cores 30. DMA Controller Core 31. Modular Scatter-Gather DMA Core 32. Scatter-Gather DMA Controller Core 33. SDRAM Controller Core 34. Tri-State SDRAM Core 35. Video Sync Generator and Pixel Converter Cores 36. Intel FPGA Interrupt Latency Counter Core 37. Performance Counter Unit Core 38. Vectored Interrupt Controller Core 39. Avalon® -ST Data Pattern Generator and Checker Cores 40. Avalon® -ST Test Pattern Generator and Checker Cores 41. System ID Peripheral Core 42. Avalon® Packets to Transactions Converter Core 43. Avalon® -ST Multiplexer and Demultiplexer Cores 44. Avalon® -ST Bytes to Packets and Packets to Bytes Converter Cores 45. Avalon® -ST Delay Core 46. Avalon® -ST Round Robin Scheduler Core 47. Avalon® -ST Splitter Core 48. Avalon® -MM DDR Memory Half Rate Bridge Core 49. Intel FPGA GMII to RGMII Converter Core 50. Intel FPGA MII to RMII Converter Core 51. HPS GMII to TSE 1000BASE-X/SGMII PCS Bridge Core Intel® FPGA IP 52. Intel FPGA HPS EMAC to Multi-rate PHY GMII Adapter Core 53. Intel FPGA MSI to GIC Generator Core 54. Cache Coherency Translator Intel® FPGA IP 55. Lightweight UART Core

26.4.1. Avalon Memory-Mapped Interface Signals

Table 283.  Interface Signals for Avalon® Memory-Mapped Single Port RAM
Signal Names Width (bit) Direction Description
Clock Interface
clk 1 Input Clock for Avalon® Memory-Mapped Agent.
Reset Interface
reset 1 Input Reset for Avalon® Memory-Mapped Agent.
reset_req 1 Input Optional signal to perform clock gating to memory during reset.
Avalon® Memory-Mapped Agent
address 2-26 Input Word addresses derived from log2 (memory size/(data width in byte)).
write 1 Input Asserted to indicate a write transfer.
byteenable 2, 4, 8, 16, 32, 64, 128 Input Enables specific byte lane(s) during transfers on interfaces of width greater than 8 bits. Each bit corresponds to a byte in writedata. readdata would not be affected by byteenable.
writedata 8, 16, 32, 64, 128, 256, 512, 1024 Input Data for write transfer.
read 1 Input Asserted to indicate a read transfer.
readdata 8, 16, 32, 64, 128, 256, 512, 1024 Output Data for read transfer.
Table 284.  Interface Signals for Avalon® Memory-Mapped Simple Dual Port RAM (Port 1 Write, Port 2 Read)
Signal Names Width (bit) Direction Description
Clock Interface
clk 1 Input Clock for Avalon® Memory-Mapped Agent. If dual clock is enabled, this is the clock domain for Avalon® Memory-Mapped Port1 only.
clk2 1 Input Clock for Avalon® Memory-Mapped Agent 2. Only available for dual clock mode. This is the clock domain for Avalon® Memory-Mapped Port2.
Reset Interface
reset 1 Input Reset for Avalon® Memory-Mapped Agent. If dual clock is enabled, this is the reset domain for Avalon® Memory-Mapped Port1 only.
reset2 1 Input Reset for Avalon® Memory-Mapped Agent 2. Only available for dual clock mode. This is the reset domain for Avalon® Memory-Mapped Port2.
reset_req 1 Input Optional signal to perform clock gating to memory during reset.
reset_req2 1 Input Optional signal to perform clock gating to memory during reset.
Avalon® Memory-Mapped Agent (Port1 Write only)
address 2-26 Input Word addresses derived from log2 (memory size/(data width in byte)).
write 1 Input Asserted to indicate a write transfer.
byteenable 2, 4, 8, 16, 32, 64, 128 Input Enables specific byte lane(s) during transfers on interfaces of width greater than 8 bits. Each bit corresponds to a byte in writedata. readdata would not be affected by byteenable.
writedata 8, 16, 32, 64, 128, 256, 512, 1024 Input Data for write transfer.
Avalon® Memory-Mapped Agent (Port2 Read only)
address2 2-26 Input Word addresses derived from log2 (memory size/(data width in byte)).
read2 1 Input Asserted to indicate a read transfer.
readdata2 8, 16, 32, 64, 128, 256, 512, 1024 Output Data for read transfer.
Table 285.  Interface Signals for Avalon® Memory-Mapped True Dual Port RAM
Signal Names Width (bit) Direction Description
Clock Interface
clk 1 Input Clock for Avalon® Memory-Mapped Agent. This is the clock domain for both Avalon® Memory-Mapped ports.
clk2 1 Input Clock for Avalon® Memory-Mapped Agent 2. Only available for dual clock mode. This is the clock domain for Avalon® Memory-Mapped Port2.
Reset Interface
reset 1 Input Reset for Avalon® Memory-Mapped Agent. This is the reset domain for both Avalon® Memory-Mapped ports.
reset2 1 Input Reset for Avalon® Memory-Mapped Agent 2. Only available for dual clock mode. This is the reset domain for Avalon® Memory-Mapped Port2.
reset_req 1 Input Optional signal to perform clock gating to memory during reset.
reset_req2 1 Input Optional signal to perform clock gating to memory during reset.
Avalon® Memory-Mapped Agent (Port 1)
address 2-26 Input Word addresses derived from log2 (memory size/(data width in byte)).
write 1 Input Asserted to indicate a write transfer.
byteenable 2, 4, 8, 16, 32, 64, 128 Input Enables specific byte lane(s) during transfers on interfaces of width greater than 8 bits. Each bit corresponds to a byte in writedata. readdata would not be affected by byteenable.
writedata 8, 16, 32, 64, 128, 256, 512, 1024 Input Data for write transfer.
read 1 Input Asserted to indicate a read transfer.
readdata 8, 16, 32, 64, 128, 256, 512, 1024 Output Data for read transfer.
Avalon® Memory-Mapped Agent (Port 2)
address2 2-26 Input Word addresses derive from log2 (memory size/(data width in byte)).
write2 1 Input Asserted to indicate a write transfer.
byteenable2 2, 4, 8, 16, 32, 64, 128 Input Enables specific byte lane(s) during transfers on interfaces of width greater than 8 bits. Each bit corresponds to a byte in writedata. readdata would not be affected by byteenable.
writedata2 8, 16, 32, 64, 128, 256, 512, 1024 Input Data for write transfer.
read2 1 Input Asserted to indicate a read transfer.
readdata2 8, 16, 32, 64, 128, 256, 512, 1024 Output Data for read transfer.