SDI II Intel® FPGA IP User Guide

ID 683133
Date 10/08/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.4.4. SD 20-Bit Interface for Dual/Triple Rate

For a common SD interface, the serial data format is 10 bits wide, whereas for HD or 3G, the data format is 20 bits wide, divided into two parallel 10-bit datastreams (known as Y and C).

To make the interface bit width common for all standards in the dual-rate or triple-rate SDI mode:
  • The receiver can extract the data and align them in 20-bit width
  • The transmitter can accept SD data in 20-bit width and retransmit them successfully

The timing diagrams below show a comparison of data arrangement between 10-bit and 20-bit interface.

Figure 29. SD 10-Bit Interface


  • The upper 10 bits of rx_dataout are insignificant data.
  • The lower 10 bits of rx_dataout are Luma (Y) and chroma (Cb, Cr) channels (interleaved).
  • The 1H 4L 1H 5L cadence of rx_dataout_valid repeats indefinitely (ideal).

Figure 30. SD 20-Bit Interface


  • The upper 10 bits of rx_dataout are Luma (Y) channel and the lower 10 bits are Chroma (Cb, Cr) channel.
  • The 1H 10L cadence of rx_dataout_valid repeats indefinitely (ideal).