AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

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ID 683185
Date 6/09/2020
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Document Table of Contents
Document Table of Contents x
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. ADC12DJxx00RF EVM Software and JESD204C Example Design Setup 1.4. Hardware Checkout Methodology 1.5. JESD204C Intel® FPGA IP and ADC Configurations 1.6. Test Results 1.7. Test Result Comments 1.8. Document Revision History for AN 909: JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices 1.9. Appendix
1.4. Hardware Checkout Methodology x
1.4.1. Receiver Data Link Layer 1.4.2. Receiver Transport Layer 1.4.3. Deterministic Latency (Subclass 1)
1.4.1. Receiver Data Link Layer x
1.4.1.1. Sync Header Alignment 1.4.1.2. Extended Multiblock Alignment
1. JESD204C Intel® FPGA IP and TI ADC12DJ5200RF Interoperability Report for Intel® Stratix® 10 Devices

1.4.3. Deterministic Latency (Subclass 1)

Configure the On-board Clocking option of the ADC12DJ5200RF EVM to provide periodic SYSREF to both the ADC12DJ5200RF and JESD204C Intel® FPGA IP in the FPGA with the required extended multi-block period.

Figure 4. Deterministic Latency Measurement Block Diagram

The Timestamp feature of ADC12DJ5200RF (refer to the Timestamp section of the ADC12DJ5200RF data sheet) is enabled for the data latency measurement.

The deterministic latency measurement block checks the deterministic latency by measuring the number of link clock counts between the assertion of the TMSTP and the logic OR of the LSB bit of all sample at the output of the RX JESD204C Intel® FPGA IP after the link is established or assertion of j204c_rx_avst_valid.

Figure 5. Deterministic Latency Measurement Timing Diagram

With the setup in Figure 2, three test cases were defined to prove deterministic latency. The JESD204C Intel® FPGA IP does continuous SYSREF detection.

Table 4.  Deterministic Latency Test Cases
Test Case Objective Description Passing Criteria
DL.1 Check the FPGA SYSREF single detection. Check that the FPGA detects the first rising edge of SYSREF pulse.
  • Read the status of sysref_singledet (bit[2]) identifier in rx_sysref_ctrl register at address 0x54.
  • Read the status of sysref_lemc_err (bit[0]) identifier in the rx_err register at address 0x60.
  • The value of sysref_singledet identifier should be zero.
  • The value of sysref_lemc_err identifier should be zero.
DL.2 Check the SYSREF capture. Check that FPGA and ADC capture SYSREF correctly and restart the LEM counter. Both FPGA and ADC are also repetitively reset.
  • Read the value of rbd_count (bit[18:10]) identifier in rx_status register at address 0x80.
If the SYSREF is captured correctly and the LEM counter restarts, for every reset, the rbd_count value should only drift within 1 to 2 link clocks to accommodate for worst case power cycle variation.
DL.3 Check the data latency during user data phase. Check that the data latency is consistent for every FPGA and ADC reset and power cycle (using the Timestamp feature of ADC12DJ5200RF shown in Figure 4).
  • The deterministic latency measurement block in Figure 2 has a counter to measure the link clock count.
The link clock count value should only drift within 1 to 2 link clocks for at least 10 power cycle tests.
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