DisplayPort Intel® FPGA IP Release Notes

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Date 4/01/2024
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1. DisplayPort Intel® FPGA IP Release Notes
1. DisplayPort Intel® FPGA IP Release Notes x
1.1. DisplayPort Intel® FPGA IP v20.0.1 1.2. DisplayPort Intel® FPGA IP v20.0.0 1.3. DisplayPort Intel® FPGA IP v19.4.0 1.4. DisplayPort Intel® FPGA IP v19.3.0 1.5. DisplayPort Intel® FPGA IP v19.1 1.6. DisplayPort Intel® FPGA IP v18.1 Update 1 1.7. DisplayPort Intel® FPGA IP v18.1 1.8. DisplayPort Intel® FPGA IP v18.0 1.9. Intel FPGA DisplayPort IP Core v17.1 1.10. DisplayPort IP Core v17.0 1.11. DisplayPort IP Core v16.1 1.12. DisplayPort IP Core v16.0 1.13. DisplayPort IP Core v15.1 1.14. DisplayPort IP Core v15.0 1.15. DisplayPort IP Core v14.1 1.16. DisplayPort Intel® FPGA IP User Guide Archives 1.17. DisplayPort Arria® 10 FPGA IP Design Example User Guide Archives 1.18. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.19. DisplayPort Stratix® 10 FPGA IP Design Example User Guide Archives
1. DisplayPort Intel® FPGA IP Release Notes

1.15. DisplayPort IP Core v14.1

Table 23.  v14.1 December 2014
Description Impact
Added multi-stream support (MST, 1 to 4 source and sink streams). You can access this feature using these parameters:
  • Support MST
  • Max stream count
These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added support for 4Kp60 resolution.
Removed support for double reference clocks—162 MHz and 270 MHz—for transceiver clocking.
Updated the design example with pixel clock recovery feature and 4Kp60 support.
Added new signals.
Added new source registers:
  • 0×00a0 (DPTX_MST_CONTROL1)
  • 0×00a2 (DPTX _MST_VCPTAB0)
  • 0×00a3 (DPTX _MST_VCPTAB
  • 0×00a3 (DPTX _MST_VCPTAB1)
  • 0×00a4 (DPTX _MST_VCPTAB2)
  • 0×00a5 (DPTX _MST_VCPTAB3)
  • 0×00a6 (DPTX _MST_VCPTAB4)
  • 0×00a7 (DPTX _MST_VCPTAB5)
  • 0×00a8 (DPTX _MST_VCPTAB6)
  • 0×00a9 (DPTX _MST_VCPTAB7)
  • 0×00aa (DPTX _MST_TAVG_TS)
Added new sink registers:
  • 0×0006 (DPRX_BER_CNTI0)
  • 0×0007 (DPRX_BER_CNTI1)
  • 0×00a0 (DPRX_MST_CONTROL1)
  • 0×00a1 (DPRX_MST_STATUS1)
  • 0×00a2 (DPRX _MST_VCPTAB0)
  • 0×00a3 (DPRX _MST_VCPTAB1)
  • 0×00a4 (DPRX _MST_VCPTAB2)
  • 0×00a5 (DPRX _MST_VCPTAB3)
  • 0×00a6 (DPRX _MST_VCPTAB4)
  • 0×00a7 (DPRX _MST_VCPTAB5)
  • 0×00a8 (DPRX _MST_VCPTAB6)
  • 0×00a9 (DPRX _MST_VCPTAB7)
Changed the value of the following register bits:
  • Source register
    • 0×0000 - Bits RX_LINK_RATE
    • 0×0001 - Bits RX_LINK_RATE
    • 0×0002 - Bits RSTI3, RSTI2, RSTI1, RSTI0
  • Sink register
    • 0×0000 - Bits TX_LINK_RATE and ENHANCED_FRAME
Table 24.  DisplayPort IP Core Signal ChangesSignals added or modified in version 14.1.
Old Signal Name New Signal Name Notes
— clk_cal Calibration clock for transceiver management interface
— tx_link_rate_8bits Main link rate expressed in multiples of 270Mbps
— rx_link_rate_8bits
— txN_video_in (N=1,2,3) TX signals for Stream 1, 2 and 3
— txN_vid_clk (N=1,2,3)
— txN_audio (N=1,2,3)
— txN_audio_clk (N=1,2,3)
— txN_ss (N=1,2,3)
— txN_msa_conduit (N=1,2,3)
— rxN_video_out (N=1,2,3) RX signals for Stream 1, 2 and 3
— rxN_vid_clk (N=1,2,3)
— rxN_audio (N=1,2,3)
— rxN_ss (N=1,2,3)
— rxN_msa_conduit (N=1,2,3)
— rxN_stream (N=1,2,3)
tx_xcvr_clkout tx_ss_clk —
rx_xcvr_clkout rx_ss_clk —
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