Intel® Stratix® 10 GX Transceiver Signal Integrity Development Kit User Guide

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ID 683206
Date 2/21/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System 7. Board Update Portal A. Additional Information B. Revision History
1. Overview x
1.1. General Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Board
2. Getting Started x
2.1. Installing the Quartus Prime software 2.2. Installing the Development Board 2.3. Installing the Intel® FPGA Download Cable Driver
3. Development Board Setup x
3.1. Setting up the Development Board 3.2. Factory Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. Intel® Stratix® 10 GX FPGA 4.3. MAX V CPLD System Controller 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. User Input-Output Components 4.8. Clock Circuits 4.9. Transceiver Channels 4.10. Communication Ports 4.11. Flash Memory
4.4. FPGA Configuration x
4.4.1. FPGA Programming over Embedded Intel® FPGA Download Cable II 4.4.2. FPGA Programming from Flash Memory 4.4.3. FPGA Programming over External Intel® FPGA Download Cable II
4.7. User Input-Output Components x
4.7.1. User-Defined Pushbuttons 4.7.2. User-Defined DIP Switch 4.7.3. User-Defined LEDs 4.7.4. Character LCD
4.8. Clock Circuits x
4.8.1. Transceiver Dedicated Clocks 4.8.2. General-Purpose Clocks 4.8.3. Embedded Intel® FPGA Download Cable II Clock
5. System Power x
5.1. Power Guidelines 5.2. Power Supply 5.3. Power Management 5.4. Power Distribution System 5.5. Thermal Limitations and Protection Guidelines
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The FMCA Tab 6.3.6. The FMCB Tab 6.3.7. The LPBK Tab 6.3.8. The MXP Tab 6.3.9. The SMA Tab 6.3.10. The QSFP and SFP+ Tab 6.3.11. The CFP4 Tab 6.3.12. Power Monitor 6.3.13. Clock Controller
7. Board Update Portal x
7.1. Connecting to the Board Update Portal 7.2. Using the Board Update Portal
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Information
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
B. Revision History x
B.1. User Guide Revision History
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
7. Board Update Portal
A. Additional Information
B. Revision History

4.9. Transceiver Channels

The Intel® Stratix® 10 GX transceiver signal integrity development kit dedicates 78 channels from both the left and right sides of the device. Transceiver channels are allocated as shown in the table below.

Table 15.  Stratix 10 GX FPGA Transceiver Channels
Transceiver Channel Data Rate Number of Channels
2.4 mm RF Platinum channel 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 1
2.4 mm RF Gold channel 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 1
2.4 mm RF channels 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 4
MXP connector 0 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 4
MXP connector 1 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 4
MXP connector 2 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 4
CFP4 Optical Interface 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 4
QSFP28 0 Optical Interface 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 4
QSFP28 1 Optical Interface 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 4
SFP+ 0 Optical Interface 14 Gbps 1
SFP+ 1 Optical Interface 14 Gbps 1
FMC A Interface 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 24
FMC B Interface 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 16
External loopback Interface 17.4 Gbps or 28.3 Gbps (applies to GXT channels only) 6
Figure 10. Stratix 10 GX FPGA Transceiver Usage Block Diagram
Table 16.  2.4 mm RF Interface
Schematic Signal Name Stratix 10 FPGA Pin Number Description
GXB_4C_TXp/n[5:0] Positive pin location increases from index 0: BJ4, BF5, BG3, BE3, BF1, BC3 2.4 mm RF GXB Transmitter
GXBR_4C_RXp/n[5:0] Positive pin location increases from index 0: BH9, BJ7, BG7, BE7, BC7, BD5 2.4 mm RF GXB Receiver
Table 17.  MXP Interface
Schematic Signal Name Stratix 10 FPGA Pin Number Description
GXBL_4D_TXp/n[1:0][4:3] Positive pin location increases from index 0: BD1, BA3, AW3, AY1 MXP 1 GXB Transmitter
GXBL_4D_RXp/n[1:0][4:3] Positive pin location increases from index 0: BA7, BB5, AY5, AU7 MXP 1 GXB Receiver
GXBL_4E_TXp/n[1:0][4:3] Positive pin location increases from index 0: AV1, AR3, AP1, AN3 MXP 2 GXB Transmitter
GXBL_4E_RXp/n[1:0][4:3] Positive pin location increases from index 0: AR7, AT5, AN7, AM5 MXP 2 GXB Receiver
GXBL_4F_TXp/n[1:0][4:3] Positive pin location increases from index 0: AK1, AL3, AJ3, AF1 MXP 3 GXB Transmitter
GXBL_4F_RXp/n[1:0][4:3] Positive pin location increases from index 0: AL7, AH5, AF5, AG7 MXP 3 GXB Receiver
Figure 11. MXP connector pin function mapping
Table 18.  Optical Modules Interface
Schematic Signal Name Intel® Stratix® 10 FPGA Pin Number Description
GXBL_1C_TXp/n[1:0][4:3] Positive pin location increases from index 0: BJ46, BF45, BE47, BF49 CFP4 GXB Transmitter
GXBL_1C_RXp/n[1:0][4:3] Positive pin location increases from index 0: BH41, BJ43, BE43, BC43 CFP4 GXB Receiver
GXBL_1D_TXp/n[1:0][4:3] Positive pin location increases from index 0: BD49, BA47, AW47, AY49 QSFP28 0 GXB Transmitter
GXBL_1D_RXp/n[1:0][4:3] Positive pin location increases from index 0: BA43, BB45, AY45, AU43 QSFP28 0 GXB Receiver
GXBL_1E_TXp/n[1:0][4:3] Positive pin location increases from index 0: AV49, AR47, AP49, AN47 QSFP28 1 GXB Transmitter
GXBL_1E_RXp/n[1:0][4:3] Positive pin location increases from index 0: AR43, AT45, AN43, AM45 QSFP28 1 GXB Receiver
GXBL_1K_TXp/n 0/3 Positive pin location increases from index 0: AE47, AA47 SFP+ 0/1 GXB Transmitter
GXBL_1K_RXp/n 0/3 Positive pin location increases from index 0: AC43, AB45 SFP+ 0/1 GXB Receiver
Table 19.  FMC Interface
Schematic Signal Name Intel® Stratix® 10 FPGA Pin Number Description
FAC2Mp/n[23:0] Positive pin location increases from index 0: AE3, AC3, AD1, AA3, AB1, W3, Y1, V1, U3, T1, P1, R3, M1, N3, K1, L3, H1, J3, F1, G3, D1, E3, C3, B5 FMC A GXB Transmitter
FAM2Cp/n[23:0] Positive pin location increases from index 0: AC7, AD5, AA7, AB5, W7, Y5, V5, U7, T5, P5, R7, M5, N7, K5, L7, H5, J7, F5, G7, D5, E7, C7, A7, B9 FMC A GXB Receiver
FBC2Mp/n[15:0] Positive pin location increases from index 0: U47, T49, P49, R47, M49, N47, K49, L47, H49, J47, F49, G47, D49, E47, C47, B45 FMC B GXB Transmitter
FBM2Cp/n[15:0] Positive pin location increases from index 0: T45, P45, R43, M45, N43, K45, L43, H45, J43, F45, G43, D45, E43, C43, A43, B41 FMC B GXB Receiver
Table 20.  External Loopback Interface
Schematic Signal Name Intel® Stratix® 10 FPGA Pin Number Description
GXBL_1F_TXp/n[5:0] Positive pin location increases from index 0: AK49, AL47, AH49, AJ47, AF49, AG47 External loopback GXB Transmitter
GXBL_1F_RXp/n[5:0] Positive pin location increases from index 0: AL43, AH45, AJ43, AF45, AG43, AE43 External loopback GXB Receiver
Level Two Title