Quartus® Prime Standard Edition User Guide: Design Compilation

ID 683283
Date 10/22/2021
Public
Document Table of Contents

3.5.5. Auto RAM to Logic Cell Conversion

The Auto RAM to Logic Cell Conversion logic option allows Quartus® Prime Integrated Synthesis to convert small RAM blocks to logic cells if the logic cell implementation gives better quality of results. The software converts only single-port or simple-dual port RAMs with no initialization files to logic cells. You can set this option globally or apply it to individual RAM nodes. You can enable this option by turning on the appropriate option for the entire project in the Advanced Analysis & Synthesis Settings dialog box.

For Arria GX and Stratix family of devices, the software uses the following rules to determine the placement of a RAM, either in logic cells or a dedicated RAM block:

  • If the number of words is less than 16, use a RAM block if the total number of bits is greater than or equal to 64.
  • If the number of words is greater than or equal to 16, use a RAM block if the total number of bits is greater than or equal to 32.
  • Otherwise, implement the RAM in logic cells.

For the Cyclone family of devices, the software uses the following rules:

  • If the number of words is greater than or equal to 64, use a RAM block.
  • If the number of words is greater than or equal to 16 and less than 64, use a RAM block if the total number of bits is greater than or equal to 128.
  • Otherwise, implement the RAM in logic cells.