Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes

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ID 683289
Date 9/28/2020
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1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes
1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes x
1.1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v21.0.0 1.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v20.0.0 1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v19.1.0 1.4. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives 1.5. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design Example User Guide Archives
1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Release Notes

1.1. Low Latency E-Tile 40G Ethernet Intel® FPGA IP v21.0.0

Table 1.  v21.0.0 2020.09.28
Intel® Quartus® Prime Version Description Impact
20.3 Updated the reconfig_address signal width from 21-bit address to a 20-bit address. Removed deprecated bit [21].
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