Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 9/30/2022
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 3D LUT Intel® FPGA IP 9. AXI-Stream Broadcaster Intel® FPGA IP 10. Chroma Key Intel® FPGA IP 11. Chroma Resampler Intel® FPGA IP 12. Clipper Intel® FPGA IP 13. Clocked Video Input Intel® FPGA IP 14. Clocked Video to Full-Raster Converter Intel® FPGA IP 15. Clocked Video Output Intel® FPGA IP 16. Color Space Converter Intel® FPGA IP 17. Deinterlacer Intel® FPGA IP 18. FIR Filter Intel® FPGA IP 19. Frame Cleaner Intel® FPGA IP 20. Full-Raster to Clocked Video Converter Intel® FPGA IP 21. Full-Raster to Streaming Converter Intel® FPGA IP 22. Generic Crosspoint Intel® FPGA IP 23. Genlock Signal Router Intel® FPGA IP 24. Guard Bands Intel® FPGA IP 25. Interlacer Intel® FPGA IP 26. Mixer Intel® FPGA IP 27. Pixels in Parallel Converter Intel® FPGA IP 28. Scaler Intel® FPGA IP 29. Stream Cleaner Intel® FPGA IP 30. Switch Intel® FPGA IP 31. Tone Mapping Operator Intel® FPGA IP 32. Test Pattern Generator Intel® FPGA IP 33. Video Frame Buffer Intel® FPGA IP 34. Video Streaming FIFO Intel® FPGA IP 35. Video Timing Generator Intel® FPGA IP 36. Warp Intel® FPGA IP 37. Design Security 38. Document Revision History for Video and Vision Processing Suite User Guide

27.5. Pixels in Parallel Converter IP Software API

The IP includes software for run-time control. The IP does not fit any of the generic device models provided by the Nios II HAL and it exposes a set of dedicated accessors to the control and status registers. The IP driver structure inherits the base driver structure so all common methods defined in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_pip_conv_regs.h

Include file: intel_vvp_pip_conv.h

Table 428.  Pixels in Parallel IP API Reference
Name Description
intel_vvp_ pip_conv _init Initialize the pixels in parallel instance
Intel_vvp_core_* .Accessors defined in Video and Vision Processing IPs Software Programming Model . Writable when Lite is on. Readable when Lite is off and Debug features is on.
intel_vvp_pip_conv_get_lite_mode Returns if Lite mode is on
intel_vvp_pip_conv_get_debug_enabled Returns if Lite mode is on
intel_vvp_pip_conv_is_running Returns if the IP is processing data
intel_vvp_pip_conv_get_status Reads the status register

intel_vvp_pip_conv_init

Prototype
int intel_vvp_pip_conv_init(intel_vvp_pip_conv_instance *instance, intel_vvp_core_base base);
Description

Initializes a pip_conv instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance does not fully initialized and should not be used further by the application if returning a non-zero error code.

Arguments

instance – pointer to the intel_vvp_pip_conv_instance software driver instance structure

base – base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the TPG product ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpTpgRegMapVersionErr if the register map is not supported

intel_vvp_pip_conv_get_lite_mode

Prototype
bool intel_vvp_pip_conv_get_lite_mode(intel_vvp_pip_conv_instance *instance);
Description
Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_pip_conv_instance fully initialized
Arguments

instance – pointer to the intel_vvp_pip_conv_instance software driver instance structure

Returns

true in case of success because the IP does not have an agent interface when parameterized in full mode

intel_vvp_pip_conv_get_debug_enabled

Prototype
bool intel_vvp_pip_get_debug_enabled(intel_vvp_pip_conv_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_pip_conv_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_pip_conv_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_pip_conv_is_running

Prototype
bool intel_vvp_pip_conv_is_running(intel_vvp_ pip_conv_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_pip_conv_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_pip_conv_instance software driver instance structure

Returns

True is the IP is currently generating an output field, false when disabled and/or between two fields

intel_vvp_pip_conv_get_status

Prototype
uint8_t intel_vvp_pip_conv_get_status(intel_vvp_tpg_instance* instance);
Description

Reads and returns the STATUS register. The instance must be a valid intel_vvp_pip_conv_instance fully initialized.

Arguments

instance – pointer to the intel_vvp_pip_conv_instance software driver instance structure

Returns

The value read from the status register