Parallel Add

This IP calculates the sum of the inputs.

Turn on Wide adder architecture (under the Options tab) for an architecture optimized for very wide bit-widths. This architecture reduces both resource utilization and latency. The wide adder architecture requires that all inputs share the same format.

Multiply

This IP multiplies the two inputs. The IP provides architectures optimized for multiplying wide operands (tens to thousands of bits), if you turn on Wide multiplier architecture under the Options tab.

If the IP core cannot represent the product of the inputs in the output format you chose, the result is undefined.

Modular Multiply

This IP implements a modular multiplier using Barrett’s algorithm. The IP inputs A, B and the modulus M and returns AB % M. A, B and M share the same bit-width and they are unsigned. For each set of inputs A, B and M, the IP also requires you to provide R, which is an approximation to the reciprocal of M. R is to be provided on width+1 bits and is computed as R=saturate(floor(4^width/M)). The IP requires that M is in the interval [2^(width-1), (2^width)-1], and therefore requires that the most significant bit of M is 1.

The IP also allows you to instantiate this modular multiplier for a fixed modulus value. You can input the modulus value using the provided text field. You can select the base used for expressing the modulus value. The modulus value must also be in the interval [2^(width-1), (2^width)-1].

For example, when width=8 the allowed modulus values are [128, 255].

Divide

This IP core produces the result of the first input, numerator, divided by the second input, denominator. The Divide IP core has a fixed-point output. You can control the number of significant bits in the output by adjusting the output data format. If you reduce the number of bits in the output, the divider uses fewer resources.

The LSB in the divider's output is faithfully rounded. Use the Integer Divide IP core to obtain true equivalence to a truncating CPU integer divider. The faithfully rounded result has an accuracy of one unit in the last place, where one unit in the last place is the weight of the LSB. For example, if the output format has zero fraction bits, the weight of the LSB is 2^0=1. If the result is 3.2, the IP core can either return 3 or 4, where both results are equally valid.

Square Root

The output is faithfully rounded. The faithfully rounded result has an accuracy of one unit in the last place, where one unit in the last place is the weight of the LSB. For example, if the output format has zero fraction bits, the weight of the LSB is 2^0=1. If the result is 3.2, the IP core can either return 3 or 4, where both results are equally valid.

Integer Divide

This IP core produces the result of the first input, numerator, divided by the second input, denominator. The Divide IP core has a fixed-point output. You can control the number of significant bits in the output by adjusting the output data format. If you reduce the number of bits in the output, the divider uses fewer resources.

The Integer Divide IP core offers true equivalence to a truncating CPU integer divider.

Simple Counter

This IP core maintains a counter and produces the counter value each cycle.The value of the counter increments by the positive step value every cycle for which the enable input is high.

The counter limit is its rollover value. The IP core sizes a counter to accommodate a value one less than the limit you specify. For example, a limit of 65,536 specifies a 16-bit counter. If the start value is 0 and the step value is 1, the counter rolls over from 65,535 to 0.

The limit must be equal to start plus an integer multiple of step.

Loadable Counter

This IP core maintains a counter and produces the counter value each cycle.T

You configure the counter with start value, step and limit values. You specify an initial configuration at setup time using the IP GUI. The counter always uses this configuration on reset. The counter allows changing configurations at runtime. To set new values at runtime, change the corresponding input signals (start, step and limit) and hold the sload signal high for one cycle.

The initial reset initializes the counter to the setup start value. Then counter value gets incremented by the step value in every cycle for which the enable signal is high.

You can specify the counter width and its sign. These values determine the range of the counter [minValue, maxValue]. If the counter type is w-bit unsigned, minValue=0 and maxValue=(2^width) – 1. If the counter type is w-bit signed, minValue=-2^(width-1) and maxValue=(2^(width-1))-1.

For positive limit values, and when enable is high, the next value of the counter is computed as (value + step) % limit. % denotes the remainder operation.

For example, for a 5-bit signed counter, which is loaded with start value=7, step=3 and limit=13, the counter values are 10, 0, 3, 6, 9, 12, 2, 5, 8.

When the limit is negative, the next counter value is minValue + ((value + step) % (maxValue+1)). As the next counter value exceeds the set limit, the next counter value is computed as the difference between this value and the limit.

For example, for a 5-bit signed counter, which is loaded with start value=13, step=3 and limit=-10 the next counter value is -16 + ((13+3)%16) = -16. The value after that is -16+3=-13. The next value -13+3=-10 reaches the limit, and the next counter value is set to -10-(-10)=0. The next values are 3, 6, 9, 12, 15. The next counter value after 15 is (-16 + ((15+3)%16))=-14. The value after is -11. The next value is (-11+3)-(-10)=2.

The loadable counter requires that step is a positive value. The IP requires the initial start value and limit are also positive values, and that their difference be a multiple of the step size.