Serial Lite III Streaming Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683341
Date 11/01/2021
Public
Document Table of Contents

2.3.3. Clocking Scheme

The following diagrams show the clocking scheme for the design example.
Figure 12. Clocking Scheme for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Simplex Core in Standard Clocking Mode
Figure 13. Clocking Scheme for Intel® Stratix® 10 H-tile and L-tile Serial Lite III Streaming Duplex Core in Standard Clocking Mode