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1. List of Abbreviations
2. Introduction
3. Intel® Stratix® 10 FPGA Package Mechanical Design
4. Intel® Stratix® 10 FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Stratix® 10 Devices
6. Power and Thermal Calculator (PTC) for Intel® Stratix® 10 Devices
7. Maximum Power and Typical Power
8. Document Revision History for AN 943: Thermal Modeling for Intel® Stratix® 10 FPGAs with the Intel® FPGA Power and Thermal Calculator
6.1. Device Selection
6.2. Logic Design Information
6.3. Thermal Settings and Parameters
6.4. Thermal Design Optimization
6.5. Updating Thermal Parameters
6.6. Intel® Stratix® 10 Device with PCIe Thermal Design Example 1
6.7. Heat Sink
6.8. Intel® Stratix® 10 Device with PCIe Thermal Design Example 2 (Alternate Method)
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3. Intel® Stratix® 10 FPGA Package Mechanical Design
An Intel® Stratix® 10 FPGA comes in a ball grid array (BGA) package with a copper integrated heat spreader (IHS). It can contain up to three types of dies, as follows:
- Core fabric die. This is the main FPGA die, which contains the basic logic resources, and is available in various sizes and grades. All Intel® Stratix® 10 devices (except for the 1SG10MH_U1) have a single core fabric die.
- Transceiver die. Transceiver dies are offered in four types: L-Tile, H-Tile, E- Tile and P-tile. Packages with E-Tile also have one H-Tile. Each transceiver tile type supports certain protocols and transceiver speeds. Depending on the package size, an Intel® Stratix® 10 device can support up to six transceiver dies. All dies have 24 transceiver channels, except for the P-tile dies which have 16 channels.
- HBM die. The HBM die comes in two memory-die stack configurations: 4 high or 8 high. Not all Intel® Stratix® 10 packages have HBM, however those that do can have either one or two HBMs.