Intel® FPGA Streaming Video Protocol Specification

ID 683397
Date 5/15/2024
Public
Document Table of Contents

2.2.7. Packing with Multiple Pixels in Parallel

The Intel FPGA streaming video protocol specifies a packing scheme for multiple pixels in parallel.
2 Pixels in Parallel, 30 bit RGB video packetThe second pixel begins at bit 32 to maintain byte-alignment.

The figures show more examples of pixel packing for 1, 2 and 4 pixels in parallel.

Figure 28. TDATA RGB Layout: One pixel in parallel configurationNumbers refer to pixel LSBs
Figure 29. TDATA RGB Layout: Two pixels in parallel configurationNumbers refer to pixel LSBs
Figure 30. TDATA RGB Layout: Four pixels in parallel configurationNumbers refer to pixel LSBs