E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468
Date 2/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. About E-Tile Hard IP User Guide 2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core 3. About the E-Tile CPRI PHY Intel® FPGA IP 4. Supported Tools 5. E-tile Hard IP User Guide Archives
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Supported Features 2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview 2.3. IP Core Device Family and Speed Grade Support 2.4. IP Core Verification 2.5. Resource Utilization 2.6. Release Information 2.7. Getting Started 2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters 2.9. Functional Description 2.10. Reset 2.11. Interfaces and Signals 2.12. Register Descriptions 2.13. Document Revision History for the E-Tile Hard IP for Ethernet Intel FPGA IP Core
2.3. IP Core Device Family and Speed Grade Support x
2.3.1. E-Tile Hard IP for Ethernet Intel FPGA IP Device Family Support 2.3.2. E-Tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support
2.4. IP Core Verification x
2.4.1. Simulation Environment 2.4.2. Compilation Checking 2.4.3. Hardware Testing
2.7. Getting Started x
2.7.1. Installing and Licensing Intel® FPGA IP Cores 2.7.2. Specifying the IP Core Parameters and Options 2.7.3. Generated File Structure 2.7.4. Integrating Your IP Core in Your Design 2.7.5. IP Core Testbenches 2.7.6. Compiling the Full Design
2.7.1. Installing and Licensing Intel® FPGA IP Cores x
2.7.1.1. Intel® FPGA IP Evaluation Mode
2.7.4. Integrating Your IP Core in Your Design x
2.7.4.1. Channel Placement 2.7.4.2. Pin Assignments 2.7.4.3. Clock Requirements 2.7.4.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.4.5. SDC for Multiple E-Tile Instances
2.7.4.1. Channel Placement x
2.7.4.1.1. Guidelines and Restrictions for 24-bonded Channels Variant 2.7.4.1.2. Guidelines and Restrictions for 16-bonded Channels Variant
2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters x
2.8.1. Parameter Editor Parameters 2.8.2. RTL Parameters
2.9. Functional Description x
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC 2.9.2. 1588 Precision Time Protocol Interfaces 2.9.3. PCS, OTN, FlexE, and Custom PCS Modes 2.9.4. Auto-Negotiation and Link Training 2.9.5. TX and RX RS-FEC 2.9.6. PMA Direct Mode 2.9.7. Dynamic Reconfiguration 2.9.8. Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example 2.9.9. Ethernet Adaptation Flow for 100G (CAUI-2) PAM4 <---> 100G (CAUI-4) NRZ Dynamic Reconfiguration Design Example 2.9.10. Ethernet Adaptation Flow with PTP or with External AIB Clocking 2.9.11. Ethernet Adaptation Flow with Non-external AIB Clocking
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC x
2.9.1.1. MAC TX Datapath 2.9.1.2. MAC RX Datapath 2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 2.9.1.4. Pause Control and Generation Interface 2.9.1.5. Pause Control Frame Filtering 2.9.1.6. Link Fault Signaling 2.9.1.7. Order of Ethernet Transmission
2.9.1.1. MAC TX Datapath x
2.9.1.1.1. TX Preamble, Start, and SFD Insertion 2.9.1.1.2. Source Address Insertion 2.9.1.1.3. Length/Type Field Processing 2.9.1.1.4. Frame Padding 2.9.1.1.5. Frame Check Sequence (CRC-32) Insertion 2.9.1.1.6. Inter-Packet Gap Generation and Insertion
2.9.1.2. MAC RX Datapath x
2.9.1.2.1. RX Preamble Processing 2.9.1.2.2. RX Strict SFD Checking 2.9.1.2.3. RX FCS Checking 2.9.1.2.4. RX Malformed Packet Handling 2.9.1.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 2.9.1.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 2.9.1.2.7. Inter-Packet Gap
2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
2.9.1.3.1. Conditions Triggering XOFF Frame Transmission 2.9.1.3.2. Conditions Triggering XON Frame Transmission
2.9.1.6. Link Fault Signaling x
2.9.1.6.1. Determining Link Fault Condition
2.9.2. 1588 Precision Time Protocol Interfaces x
2.9.2.1. Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP 2.9.2.2. PTP Timestamp Accuracy 2.9.2.3. PTP Transmit Functionality 2.9.2.4. PTP Receive Functionality 2.9.2.5. External Time-of-Day Module for 1588 PTP Variations 2.9.2.6. PTP Timestamp and TOD Formats 2.9.2.7. 10G/25G TX and RX Unit Interval Adjustment 2.9.2.8. 10G/25G TX and RX PTP Extra Latency 2.9.2.9. 100G PTP TX User Flow 2.9.2.10. 100G PTP RX User Flow 2.9.2.11. 100G RX Virtual Lane Offset Calculation for No FEC Variants 2.9.2.12. 100G UI Adjustment 2.9.2.13. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 2.9.2.14. PTP System Considerations 2.9.2.15. Logic Lock Regions Requirements for PTP Accuracy Advanced Mode
2.9.3. PCS, OTN, FlexE, and Custom PCS Modes x
2.9.3.1. PCS Only Mode 2.9.3.2. OTN Mode 2.9.3.3. FlexE Mode 2.9.3.4. Custom PCS Mode
2.10. Reset x
2.10.1. Reset Sequence
2.10.1. Reset Sequence x
2.10.1.1. Reset Sequence with External AIB Clocking
2.11. Interfaces and Signals x
2.11.1. TX MAC Interface to User Logic 2.11.2. RX MAC Interface to User Logic 2.11.3. TX PCS Interface to User Logic 2.11.4. RX PCS Interface to User Logic 2.11.5. FlexE and OTN Mode TX Interface 2.11.6. FlexE and OTN Mode RX Interface 2.11.7. TX Custom PCS Interface to User Logic 2.11.8. RX Custom PCS Interface to User Logic 2.11.9. PMA Direct Interface 2.11.10. Custom Rate Interface 2.11.11. Deterministic Latency Interface 2.11.12. 1588 PTP Interface 2.11.13. Ethernet Link and Transceiver Signals 2.11.14. Reconfiguration Interfaces and Signals 2.11.15. Miscellaneous Status and Debug Signals 2.11.16. Reset Signals 2.11.17. Clocks
2.11.14. Reconfiguration Interfaces and Signals x
2.11.14.1. Ethernet Reconfiguration Interfaces 2.11.14.2. Transceiver Reconfiguration Interfaces 2.11.14.3. RS-FEC Reconfiguration Interfaces 2.11.14.4. PTP Reconfiguration Interfaces
2.11.17. Clocks x
2.11.17.1. Asynchronous Adapter Clock in 10G/25G Mode 2.11.17.2. Asynchronous Adapter Clock in 100G Mode 2.11.17.3. Clock Network Use Cases
2.11.17.3. Clock Network Use Cases x
2.11.17.3.1. Single 25G Ethernet Channel (with FEC) 2.11.17.3.2. Single 10G Ethernet Channel (without FEC) 2.11.17.3.3. Four 25G Ethernet Channels (with FEC) within a Single FEC Block 2.11.17.3.4. Ethernet 25G x 4 (FEC Off) 2.11.17.3.5. 10G/25G Ethernet Channel with Basic PTP Accuracy Mode 2.11.17.3.6. 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode 2.11.17.3.7. 100G Ethernet with Aggregated FEC 2.11.17.3.8. 100G Ethernet with PTP 2.11.17.3.9. Single 25G Synchronous Ethernet Channel 2.11.17.3.10. Multiple 25G Synchronous Ethernet Channels
2.12. Register Descriptions x
2.12.1. Auto Negotiation and Link Training Registers 2.12.2. PHY Registers 2.12.3. TX MAC Registers 2.12.4. RX MAC Registers 2.12.5. Pause and Priority- Based Flow Control Registers 2.12.6. TX Statistics Counter Registers 2.12.7. RX Statistics Counter Registers 2.12.8. 1588 PTP Registers 2.12.9. RS-FEC Registers 2.12.10. PMA Registers
2.12.1. Auto Negotiation and Link Training Registers x
2.12.1.1. ANLT Sequencer Config 2.12.1.2. ANLT Sequencer Status 2.12.1.3. Auto Negotiation Config Register 1 2.12.1.4. Auto Negotiation Config Register 2 2.12.1.5. Auto Negotiation Status Register 2.12.1.6. Auto Negotiation Config Register 3 2.12.1.7. Auto Negotiation Config Register 4 2.12.1.8. Auto Negotiation Config Register 5 2.12.1.9. Auto Negotiation Config Register 6 2.12.1.10. Auto Negotiation Status Register 1 2.12.1.11. Auto Negotiation Status Register 2 2.12.1.12. Auto Negotiation Status Register 3 2.12.1.13. Auto Negotiation Status Register 4 2.12.1.14. Auto Negotiation Status Register 5 2.12.1.15. AN Channel Override 2.12.1.16. Consortium Next Page Override 2.12.1.17. Consortium Next Page Link Partner Status 2.12.1.18. Link Training Config Register 1 2.12.1.19. Link Training Status Register 1 2.12.1.20. Link Training Config Register for Lane 0 2.12.1.21. Link Training Config Register for Lane 1 2.12.1.22. Link Training Config Register for Lane 2 2.12.1.23. Link Training Config Register for Lane 3
2.12.2. PHY Registers x
2.12.2.1. PHY Module Revision ID 2.12.2.2. PHY Scratch Register 2.12.2.3. Loopback Mode 2.12.2.4. PHY Configuration 2.12.2.5. Reset Sequencer RS-FEC Disable 2.12.2.6. RX CDR PLL Locked 2.12.2.7. TX Datapath Ready 2.12.2.8. Frame Errors Detected 2.12.2.9. Clear Frame Errors 2.12.2.10. RX PCS Status for AN/LT 2.12.2.11. PCS Error Injection 2.12.2.12. Alignment Marker Lock 2.12.2.13. Change in RX PCS Deskew Status 2.12.2.14. BER Count 2.12.2.15. Transfer Ready (AIB reset) Status for EHIP, ELANE, and PTP Channels 2.12.2.16. EHIP, ELANE, and RS-FEC Reset Status 2.12.2.17. PCS Virtual Lane 0 2.12.2.18. PCS Virtual Lane 1 2.12.2.19. PCS Virtual Lane 2 2.12.2.20. PCS Virtual Lane 3 2.12.2.21. Recovered Clock Frequency in KHz 2.12.2.22. TX Clock Frequency in KHz 2.12.2.23. Configuration Fields for TX PLD 2.12.2.24. Status for TX PLDs 2.12.2.25. Status for Dynamic Deskew Buffer 2.12.2.26. Configuration for RX PLD Block 2.12.2.27. Configuration for RX PCS 2.12.2.28. BIP Counter 0 2.12.2.29. BIP Counter 1 2.12.2.30. BIP Counter 2 2.12.2.31. BIP Counter 3 2.12.2.32. BIP Counter 4 2.12.2.33. BIP Counter 5 2.12.2.34. BIP Counter 6 2.12.2.35. BIP Counter 7 2.12.2.36. BIP Counter 8 2.12.2.37. BIP Counter 9 2.12.2.38. BIP Counter 10 2.12.2.39. BIP Counter 11 2.12.2.40. BIP Counter 12 2.12.2.41. BIP Counter 13 2.12.2.42. BIP Counter 14 2.12.2.43. BIP Counter 15 2.12.2.44. BIP Counter 16 2.12.2.45. BIP Counter 17 2.12.2.46. BIP Counter 18 2.12.2.47. BIP Counter 19 2.12.2.48. Timer Window for Hi-BER Checks 2.12.2.49. Hi-BER Frame Errors 2.12.2.50. Error Block Count 2.12.2.51. Deskew Depth 0 2.12.2.52. Deskew Depth 1 2.12.2.53. Deskew Depth 2 2.12.2.54. Deskew Depth 3 2.12.2.55. RX PCS Test Error Count
2.12.3. TX MAC Registers x
2.12.3.1. TX MAC Module Revision ID 2.12.3.2. TX MAC Scratch Register 2.12.3.3. Link Fault Configuration 2.12.3.4. IPG Words to remove per Alignment Marker Period 2.12.3.5. Maximum TX Frame Size 2.12.3.6. TX MAC Configuration 2.12.3.7. EHIP TX MAC Feature Configuration 2.12.3.8. TX MAC Source Address Lower Bytes 2.12.3.9. TX MAC Source Address Higher Bytes
2.12.4. RX MAC Registers x
2.12.4.1. RX MAC Module Revision ID 2.12.4.2. RX MAC Scratch Register 2.12.4.3. Maximum RX Frame Size 2.12.4.4. RX CRC Forwarding 2.12.4.5. Link Fault Status 2.12.4.6. RX MAC Configuration 2.12.4.7. EHIP RX MAC Feature Configuration
2.12.5. Pause and Priority- Based Flow Control Registers x
2.12.5.1. TXSFC Module Revision ID 2.12.5.2. TX SFC Scratch Register 2.12.5.3. Enable TX Pause Ports 2.12.5.4. TX Pause Request 2.12.5.5. Enable Automatic TX Pause Retransmission 2.12.5.6. Retransmit Holdoff Quanta 2.12.5.7. Retransmit Pause Quanta 2.12.5.8. Enable TX XOFF 2.12.5.9. Enable Uniform Holdoff 2.12.5.10. Set Uniform Holdoff 2.12.5.11. Lower 4 bytes of the Destination address for Flow Control 2.12.5.12. Higher 2 bytes of the Destination address for Flow Control 2.12.5.13. Lower 4 bytes of the Source address for Flow Control frames 2.12.5.14. Higher 2 bytes of the Source address for Flow Control frames 2.12.5.15. TX Flow Control Feature Configuration 2.12.5.16. Pause Quanta 0 2.12.5.17. Pause Quanta 1 2.12.5.18. Pause Quanta 2 2.12.5.19. Pause Quanta 3 2.12.5.20. Pause Quanta 4 2.12.5.21. Pause Quanta 5 2.12.5.22. Pause Quanta 6 2.12.5.23. Pause Quanta 7 2.12.5.24. PFC Holdoff Quanta 0 2.12.5.25. PFC Holdoff Quanta 1 2.12.5.26. PFC Holdoff Quanta 2 2.12.5.27. PFC Holdoff Quanta 3 2.12.5.28. PFC Holdoff Quanta 4 2.12.5.29. PFC Holdoff Quanta 5 2.12.5.30. PFC Holdoff Quanta 6 2.12.5.31. PFC Holdoff Quanta 7 2.12.5.32. RXSFC Module Revision ID 2.12.5.33. RXSFC Scratch Register 2.12.5.34. Enable RX Pause Frame Processing 2.12.5.35. Forward Flow Control Frames 2.12.5.36. Lower 4 bytes of the Destination address for RX Pause Frames 2.12.5.37. Higher 2 bytes of the Destination address for RX Pause Frames 2.12.5.38. RX Flow Control Feature Configuration
2.12.6. TX Statistics Counter Registers x
2.12.6.1. TX Statistics Registers
2.12.7. RX Statistics Counter Registers x
2.12.7.1. RX Statistics Registers
3. About the E-Tile CPRI PHY Intel® FPGA IP x
3.1. Supported Features 3.2. E-Tile CPRI PHY Intel® FPGA IP Overview 3.3. E-Tile CPRI PHY Device Family Support 3.4. Resource Utilization 3.5. Release Information 3.6. E-Tile CPRI PHY Intel FPGA IP Core Device Speed Grade Support 3.7. Getting Started 3.8. Parameter Settings 3.9. Functional Description 3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals 3.11. Registers 3.12. Document Revision History for the E-tile CPRI PHY Intel FPGA IP
3.7. Getting Started x
3.7.1. Installing and Licensing Intel® FPGA IP Cores 3.7.2. Specifying the IP Core Parameters and Options 3.7.3. Generated File Structure 3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement 3.7.5. IP Core Testbenches 3.7.6. Compiling the Full Design
3.7.1. Installing and Licensing Intel® FPGA IP Cores x
3.7.1.1. Intel® FPGA IP Evaluation Mode
3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement x
3.7.4.1. One 24.33024 Gbps channel with RS-FEC 3.7.4.2. Two 24.33024 Gbps Channel with RS-FEC 3.7.4.3. Three 24.33024 Gbps channels with RS-FEC 3.7.4.4. Four 24.33024 Gbps channels with RS-FEC 3.7.4.5. Restrictions
3.9. Functional Description x
3.9.1. CPRI PHY Functional Blocks 3.9.2. Dynamic Reconfiguration
3.9.1. CPRI PHY Functional Blocks x
3.9.1.1. E-tile Native PHY 3.9.1.2. Soft Reset Sequencer 3.9.1.3. Latency Measurement
3.9.1.3. Latency Measurement x
3.9.1.3.1. Deterministic Latency Calculation
3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals x
3.10.1. Clock Signals 3.10.2. TX MII Interface 3.10.3. RX MII Interface 3.10.4. TX 8B/10B Interface 3.10.5. RX 8B/10B Interface 3.10.6. Status Interface for 64B/66B Line Rate 3.10.7. Status Interface for 8B/10B Line Rate 3.10.8. Serial I/O Pins 3.10.9. Reconfiguration Interfaces (Avalon-MM)
3.10.9. Reconfiguration Interfaces (Avalon-MM) x
3.10.9.1. CPRI PHY Reconfiguration Interface 3.10.9.2. Transceiver Reconfiguration Interface 3.10.9.3. RS-FEC Reconfiguration Interface
3.11. Registers x
3.11.1. PHY Registers 3.11.2. CPRI PHY Registers 3.11.3. PMA Registers 3.11.4. RS-FEC Registers
3.11.3. PMA Registers x
3.11.3.1. Minimizing PMA Adaptation Time
4. Supported Tools x
4.1. E-Tile Channel Placement Tool 4.2. Ethernet Toolkit Overview 4.3. Document Revision History for the E-tile Channel Placement Tool and the Ethernet Link Inspector
4.2. Ethernet Toolkit Overview x
4.2.1. Features
1. About E-Tile Hard IP User Guide
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core
3. About the E-Tile CPRI PHY Intel® FPGA IP
4. Supported Tools
5. E-tile Hard IP User Guide Archives

2.12.7.1. RX Statistics Registers

Table 75.  Receive Side Statistics Registers

Address

Name

Description

Access

0x900

RX_FRAGMENTS_31_0

Number of received frames less than 64 bytes and reporting a CRC error (lower 32 bits)

RO

0x901

RX_FRAGMENTS_63_32

Number of received frames less than 64 bytes and reporting a CRC error (upper 32 bits)

RO

0x902

RX_JABBERS_31_0

Number of received oversized frames reporting a CRC error (lower 32 bits)

RO

0x903

RX_JABBERS_63_32

Number of received oversized frames reporting a CRC error (upper 32 bits)

RO

0x904

RX_FCSERR_31_0

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error or rx_fcs_error output signal (lower 32 bits)

RO

0x905

RX_FCSERR_63_32

Number of received packets with FCS errors. This register maintains a count of the number of pulses on the l<n>_rx_fcs_error output signal (upper 32 bits)

RO

0x906

RX_CRCERR_OKPKT_31_0

Number of received frames with a frame of length at least 64, with CRC error (lower 32 bits)

RO

0x907

RX_CRCERR_OKPKT_63_32

Number of received frames with a frame of length at least 64, with CRC error (upper 32 bits)

RO

0x908

RX_MCAST_DATA_ERR_31_0

Number of errored multicast frames received, excluding control frames (lower 32 bits)

RO

0x909

RX_MCAST_DATA_ERR_63_32

Number of errored multicast frames received, excluding control frames (upper 32 bits)

RO

0x90A

RX_BCAST_DATA_ERR_31_0

Number of errored broadcast frames received, excluding control frames (lower 32 bits)

RO

0x90B

RX_BCAST_DATA_ERR_63_32

Number of errored broadcast frames received, excluding control frames (upper 32 bits)

RO

0x90C

RX_UCAST_DATA_ERR_31_0

Number of errored unicast frames received, excluding control frames (lower 32 bits)

RO

0x90D

RX_UCAST_DATA_ERR_63_32

Number of errored unicast frames received, excluding control frames (upper 32 bits)

RO

0x90E

RX_MCAST_CTRL_ERR_31_0

Number of errored multicast control frames received (lower 32 bits)

RO

0x90F

RX_MCAST_CTRL_ERR_63_32

Number of errored multicast control frames received (upper 32 bits)

RO

0x910

RX_BCAST_CTRL_ERR_31_0

Number of errored broadcast control frames received (lower 32 bits)

RO

0x911

RX_BCAST_CTRL_ERR_63_32

Number of errored broadcast control frames received (upper 32 bits)

RO

0x912

RX_UCAST_CTRL_ERR_31_0

Number of errored unicast control frames received (lower 32 bits)

RO

0x913

RX_UCAST_CTRL_ERR_63_32

Number of errored unicast control frames received (upper 32 bits)

RO

0x914

RX_PAUSE_ERR_31_0

Number of errored pause frames received (lower 32 bits)

RO

0x915

RX_PAUSE_ERR_63_32

Number of errored pause frames received (upper 32 bits)

RO

0x916

RX_64B_31_0

Number of 64-byte received frames (lower 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x917

RX_64B_63_32

Number of 64-byte received frames (upper 32 bits), including the CRC field but excluding the preamble and SFD bytes

RO

0x918

RX_65to127B_31_0

Number of received frames between 65–127 bytes (lower 32 bits)

RO

0x919

RX_65to127B_63_32

Number of received frames between 65–127 bytes (upper 32 bits)

RO

0x91A

RX_128to255B_31_0

Number of received frames between 128 –255 bytes (lower 32 bits)

RO

0x91B

RX_128to255B_63_32

Number of received frames between 128 –255 bytes (upper 32 bits)

RO

0x91C

RX_256to511B_31_0

Number of received frames between 256 –511 bytes (lower 32 bits)

RO

0x91D

RX_256to511B_63_32

Number of received frames between 256 –511 bytes (upper 32 bits)

RO

0x91E

RX_512to1023B_31_0

Number of received frames between 512–1023 bytes (lower 32 bits)

RO

0x91F

RX_512to1023B_63_32

Number of received frames between 512 –1023 bytes (upper 32 bits)

RO

0x920

RX_1024to1518B_31_0

Number of received frames between 1024–1518 bytes (lower 32 bits)

RO

0x921

RX_1024to1518B_63_32

Number of received frames between 1024–1518 bytes (upper 32 bits)

RO

0x922

RX_1519toMAXB_31_0

Number of received frames between 1519 bytes and the maximum size defined in the MAX_RX_SIZE_CONFIG register (lower 32 bits)

RO

0x923

RX_1519toMAXB_63_32

Number of received frames between 1519 bytes and the maximum size defined in the RXMAC_SIZE_CONFIG register (upper 32 bits)

RO

0x924

RX_OVERSIZE_31_0

Number of oversized frames (frames with more bytes than the number specified in the RXMAC_SIZE_CONFIG register) received (lower 32 bits)

RO

0x925

RX_OVERSIZE_63_32

Number of oversized frames (frames with more bytes than the number specified in the RXMAC_SIZE_CONFIG register) received (upper 32 bits)

RO

0x926

RX_MCAST_DATA_OK_31_0

Number of valid multicast frames received, excluding control frames (lower 32 bits)

RO

0x927

RX_MCAST_DATA_OK_63_32

Number of valid multicast frames received, excluding control frames (upper 32 bits)

RO

0x928

RX_BCAST_DATA_OK_31_0

Number of valid broadcast frames received, excluding control frames (lower 32 bits)

RO

0x929

RX_BCAST_DATA_OK_63_32

Number of valid broadcast frames received, excluding control frames (upper 32 bits)

RO

0x92A

RX_UCAST_DATA_OK_31_0

Number of valid unicast frames received, excluding control frames (lower 32 bits)

RO

0x92B

RX_UCAST_DATA_OK_63_32

Number of valid unicast frames received, excluding control frames (upper 32 bits)

RO

0x92C

RX_MCAST_CTRL_OK_31_0

Number of valid multicast frames received, excluding data frames (lower 32 bits)

RO

0x92D

RX_MCAST_CTRL_OK_63_32

Number of valid multicast frames received, excluding data frames (upper 32 bits)

RO

0x92E

RX_BCAST_CTRL_OK_31_0

Number of valid broadcast frames received, excluding data frames (lower 32 bits)

RO

0x92F

RX_BCAST_CTRL_OK_63_32

Number of valid broadcast frames received, excluding data frames (upper 32 bits)

RO

0x930

RX_UCAST_CTRL_OK_31_0

Number of valid unicast frames received, excluding data frames (lower 32 bits)

RO

0x931

RX_UCAST_CTRL_OK_63_32

Number of valid unicast frames received, excluding data frames (upper 32 bits)

RO

0x932

RX_PAUSE_31_0

Number of received pause frames, with or without error (lower 32 bits)

RO

0x933

RX_PAUSE_63_32

Number of received pause frames, with or without error (upper 32 bits)

RO

0x934

RX_RNT_31_0

Number of received runt packets (lower 32 bits)

A run is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x935

RX_RNT_63_32

Number of received runt packets (upper 32 bits)

A run is a packet of size less than 64 bytes but greater than eight bytes. If a packet is eight bytes or smaller, it is considered a decoding error and not a runt frame, and the IP core does not flag it nor count it as a runt.

RO

0x936

RX_st_31_0

Number of RX frame starts (lower 32 bits) RO
0x937 RX_st_63_32 Number of RX frame starts (upper 32 bits) RO
0x938 RX_lenerr_31_0 Number of RX length errors (lower 32 bits) RO
0x939 RX_lenerr_63_32 Number of RX length errors (upper 32 bits) RO
0x93A RX_pfc_err_31_0 Number of RX PFC frame with CRC error (lower 32 bits) RO
0x93B RX_pfc_err_63_32 Number of RX PFC frame with CRC error (upper 32 bits) RO
0x93C RX_pfc_31_0 Number of RX PFC frames without error (lower 32 bits) RO
0x93D RX_pfc_63_32 Number of RX PFC frames without error (upper 32 bits) RO
0x93E to 0x93F Reserved
0x940 rxstat_revid Returns a 4 byte value indicating the revision of this design RO
0x941 rxstat_scratch 32 bits of scratch register space for testing RW
0x942 to 0x944 Reserved
0x945

RX_CNTR_CONFIG

Bits[2:0]: Configuration of RX statistics counters:
  • Bit[2] = 1: Freeze stats CSRs so that all RX Stats values read from the registers are from the same moment.
    • Note that the actual stats collection counters are not frozen, but because they are all 'read' at the time of the freeze, they are cleared.
    • If a shadow request is started while snapshot is active, a new capture is executed.
    • Likewise, if a shadow request is active while snapshot is asserted, a new capture is executed.
    • While either a shadow request or a capture is active, rx_shadow_on is high.
    • Snapshot and shadow requests apply to several of the RX PCS counters as well as MAC statistics
  • Bit[1] = 1:Reset the parity error bit in RX Statistics Counter Status
    • Parity error bit remains in reset until rst_rx_parity is set back to 0
  • Bit[0] = 1: Reset all RX Stats counters
    • RX stats stays in reset until reset is set back to 0
    • Reset also applies when snapshot or shadow is active, and clears the AVMM visible registers
    • rst_rx_stats does not clear the parity error bit
Bits[31:3] are Reserved. 		RW
0x946 RX_CNTR_STATUS
  • Bit[1] = 1: The CSRs for the RX Statistics are currently frozen, and holding the Stats values from the last time a shadow request was made.
  • Bit[0] = 1: A parity error was detected on at least one of the statistics counters since the last time this bit was cleared.
Bits [31:2] are Reserved. 		RO
0x947–0x95F

Reserved

  
0x960 RX_Payload_OctetsOK_31_0 Number of received payload bytes in frames with no FCS, undersized, oversized, or payload length errors. When RX VLAN/SVLAN detection is enabled, VLAN/SVLAN header bytes are also removed from the count. Use snapshot or shadow to freeze the count before reading it to avoid value change while reading the register. RO
0x961 RX_Payload_OctetsOK_63_32 RO
0x962 RX_Frame_OctetsOK_31_0 Number of received bytes in frames with no FCS, undersized, oversized, or payload length errors. Use snapshot or shadow to freeze the count before reading it to avoid value change while reading the register. RO
0x963 RX_Frame_OctetsOK_63_32 RO
Level Two Title