Integer Arithmetic Intel® FPGA IP Cores User Guide

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ID 683490
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Integer Arithmetic Intel® FPGA IP Cores 2. LPM_COUNTER (Counter) IP Core 3. LPM_DIVIDE Intel® FPGA IP Core References 4. LPM_MULT (Multiplier) IP Core 5. LPM_ADD_SUB (Adder/Subtractor) 6. LPM_COMPARE (Comparator) 7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core 8. Intel FPGA Multiply Adder IP Core 9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core 10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core 11. ALTMULT_ADD (Multiply-Adder) IP Core 12. ALTMULT_COMPLEX (Complex Multiplier) IP Core 13. ALTSQRT (Integer Square Root) IP Core 14. PARALLEL_ADD (Parallel Adder) IP Core 15. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives 16. Document Revision History for Integer Arithmetic Intel® FPGA IP Cores User Guide
2. LPM_COUNTER (Counter) IP Core x
2.1. Features 2.2. Verilog HDL Prototype 2.3. VHDL Component Declaration 2.4. VHDL LIBRARY_USE Declaration 2.5. Ports 2.6. Parameters
3. LPM_DIVIDE Intel® FPGA IP Core References x
3.1. Features 3.2. Verilog HDL Prototype 3.3. VHDL Component Declaration 3.4. VHDL LIBRARY_USE Declaration 3.5. Ports 3.6. Parameters
4. LPM_MULT (Multiplier) IP Core x
4.1. Features 4.2. Verilog HDL Prototype 4.3. VHDL Component Declaration 4.4. VHDL LIBRARY_USE Declaration 4.5. Signals 4.6. Parameters for Stratix V, Arria V, Cyclone V, and Cyclone® 10 LP Devices 4.7. Parameters for Stratix® 10, Arria® 10, and Cyclone® 10 GX Devices
4.6. Parameters for Stratix V, Arria V, Cyclone V, and Cyclone® 10 LP Devices x
4.6.1. General Tab 4.6.2. General 2 Tab 4.6.3. Pipelining Tab
4.7. Parameters for Stratix® 10, Arria® 10, and Cyclone® 10 GX Devices x
4.7.1. General Tab 4.7.2. General 2 Tab 4.7.3. Pipelining
5. LPM_ADD_SUB (Adder/Subtractor) x
5.1. Features 5.2. Verilog HDL Prototype 5.3. VHDL Component Declaration 5.4. VHDL LIBRARY_USE Declaration 5.5. Ports 5.6. Parameters
6. LPM_COMPARE (Comparator) x
6.1. Features 6.2. Verilog HDL Prototype 6.3. VHDL Component Declaration 6.4. VHDL LIBRARY_USE Declaration 6.5. Ports 6.6. Parameters
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core x
7.1. ALTECC Encoder Features 7.2. Verilog HDL Prototype (ALTECC_ENCODER) 7.3. Verilog HDL Prototype (ALTECC_DECODER) 7.4. VHDL Component Declaration (ALTECC_ENCODER) 7.5. VHDL Component Declaration (ALTECC_DECODER) 7.6. VHDL LIBRARY_USE Declaration 7.7. Encoder Ports 7.8. Decoder Ports 7.9. Encoder Parameters 7.10. Decoder Parameters
8. Intel FPGA Multiply Adder IP Core x
8.1. Features 8.2. Verilog HDL Prototype 8.3. VHDL Component Declaration 8.4. VHDL LIBRARY_USE Declaration 8.5. Signals 8.6. Parameters
8.1. Features x
8.1.1. Pre-adder 8.1.2. Systolic Delay Register 8.1.3. Pre-load Constant 8.1.4. Double Accumulator
8.1.1. Pre-adder x
8.1.1.1. Pre-adder Simple Mode 8.1.1.2. Pre-adder Coefficient Mode 8.1.1.3. Pre-adder Input Mode 8.1.1.4. Pre-adder Square Mode 8.1.1.5. Pre-adder Constant Mode
8.6. Parameters x
8.6.1. General Tab 8.6.2. Extra Modes Tab 8.6.3. Multipliers Tab 8.6.4. Preadder Tab 8.6.5. Accumulator Tab 8.6.6. Systolic/Chainout Tab 8.6.7. Pipelining Tab
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core x
9.1. Features 9.2. Verilog HDL Prototype 9.3. VHDL Component Declaration 9.4. Ports 9.5. Parameters
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core x
10.1. Features 10.2. Verilog HDL Prototype 10.3. VHDL Component Declaration 10.4. VHDL LIBRARY_USE Declaration 10.5. Ports 10.6. Parameters
11. ALTMULT_ADD (Multiply-Adder) IP Core x
11.1. Features 11.2. Verilog HDL Prototype 11.3. VHDL Component Declaration 11.4. VHDL LIBRARY_USE Declaration 11.5. Ports 11.6. Parameters
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core x
12.1. Complex Multiplication 12.2. Canonical Representation 12.3. Conventional Representation 12.4. Features 12.5. Verilog HDL Prototype 12.6. VHDL Component Declaration 12.7. VHDL LIBRARY_USE Declaration 12.8. Signals 12.9. Parameters
13. ALTSQRT (Integer Square Root) IP Core x
13.1. Features 13.2. Verilog HDL Prototype 13.3. VHDL Component Declaration 13.4. VHDL LIBRARY_USE Declaration 13.5. Ports 13.6. Parameters
14. PARALLEL_ADD (Parallel Adder) IP Core x
14.1. Feature 14.2. Verilog HDL Prototype 14.3. VHDL Component Declaration 14.4. VHDL LIBRARY_USE Declaration 14.5. Ports 14.6. Parameters
1. Integer Arithmetic Intel® FPGA IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE Intel® FPGA IP Core References
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
16. Document Revision History for Integer Arithmetic Intel® FPGA IP Cores User Guide

6.6. Parameters

The following table lists the parameters for the LPM_COMPARE IP core.

Table 20.  LPM_COMPARE IP core Parameters
Parameter Name Type Required Description
LPM_WIDTH Integer Yes Specifies the widths of the dataa[] and datab[] ports.
LPM_REPRESENTATION String No Specifies the type of comparison performed. Values are SIGNED and UNSIGNED. If omitted, the default value is UNSIGNED. When this parameter value is set to SIGNED, the comparator interprets the data input as signed two's complement.
LPM_PIPELINE Integer No Specifies the number of clock cycles of latency associated with the alb, aeb, agb, ageb, aleb, or aneb output. A value of zero (0) indicates that no latency exists, and that a purely combinational function will be instantiated. If omitted, the default value is 0 (non-pipelined).
LPM_HINT String No Allows you to specify Intel® -specific parameters in VHDL design files (.vhd). The default value is UNUSED.
LPM_TYPE String No Identifies the library of parameterized modules (LPM) entity name in VHDL design files.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and behavioral simulation purposes. The parameter editor calculates the value for this parameter.
ONE_INPUT_IS_CONSTANT String No Intel® -specific parameter. You must use the LPM_HINT parameter to specify the ONE_INPUT_IS_CONSTANT parameter in VHDL design files. Values are YES, NO, or UNUSED. Provides greater optimization if an input is constant. If omitted, the default value is NO.
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