AN 855: PCI Express* High Performance Reference Design for Intel® Cyclone® 10 GX

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ID 683504
Date 6/08/2018
Public
Document Table of Contents
Document Table of Contents x
1. PCI Express High Performance Reference Design
1. PCI Express High Performance Reference Design x
1.1. Understanding Throughput in PCI Express 1.2. Deliverables Included with the Reference Design 1.3. Reference Design Functional Description 1.4. Hardware Requirements 1.5. Software Requirements 1.6. Software Installation 1.7. Hardware Installation 1.8. Running the Software Application 1.9. Additional Chaining DMA Commands 1.10. Using SignalTap II 1.11. Performance Benchmarking Results 1.12. Document Revision History
1.1. Understanding Throughput in PCI Express x
1.1.1. Protocol Overhead 1.1.2. Throughput for Posted Writes 1.1.3. Throughput for Reads
1.3. Reference Design Functional Description x
1.3.1. Project Hierarchy IP Core Settings Intel® Quartus® Prime Settings
1.7. Hardware Installation x
1.7.1. Programming using the .sof File
1. PCI Express High Performance Reference Design

1.3.1. Project Hierarchy

Intel® Cyclone® 10 GX devices use the following directory structure:

  • The project directory contains:
    • The top-level module top.v
    • The Intel® Quartus® Prime project file top.qpf
    • The Intel® Quartus® Prime project settings file top.qsf
  • The platform folder contains all IP files.
  • The master_image folder contains a working .sof configuration file or image.
  • The driver folder contains the software application and Windows driver for this design.

IP Core Settings

The reference design supports a maximum payload size of 256 Bytes. The desired performance for received completions and requests is set to Maximum. The following tables show the settings for supported devices.

Table 1.  System Settings for PCI Express IP Core – Intel® Cyclone® 10 GX Device
Parameter Value
PCIe IP core type PCI Express hard IP
System Settings
Number of lanes x4
Lane rate Gen2 (5.0 Gbps)
Port type Native endpoint
Application interface Avalon-ST 128-bit
RX buffer credit allocation Low
Reference clock frequency 100 MHz
Hard IP Mode Gen2x4, Interface: 128-bit, 125 MHz
Enable Avalon-ST Reset output port OFF (Unchecked)
Enable byte parity ports on Avalon-ST interface OFF (Unchecked)
Enable multiple packets per cycle for the 256-bit interface OFF (Unchecked)
Enable credit consumed selection port OFF (Unchecked)
Enable Configuration Bypass (CfgBP) OFF (Unchecked)
Enable local management interface (LMI) OFF (Unchecked)
Table 2.  PCI Register Settings – Intel® Cyclone® 10 GX Device
PCI Base Address Registers (Type 0 Configuration Space)
BAR BAR Type BAR Size
0 32-bit Non-Prefetchable Memory 256 MBytes - 28 bits
1, 3, 4, 5 Disabled N/A
2 32-bit Non-Prefetchable Memory 1 KBytes - 10 bits
PCI Read-Only Registers
Register Name Value Additional Information
Vendor ID 0x1172 The Vendor ID can be either 0x1172 or 0xB0D8. This parameter has no effect on design behavior.
Device ID 0xE001 N/A
Revision ID 0x1 N/A
Class Code 0x00FF0000 N/A
Table 3.  Capabilities Parameters – Intel® Cyclone® 10 GX Device
Capability Registers
Device Capabilities
Maximum payload size 256 Bytes
Number of tags supported 32
Completion timeout range ABCD
Implement completion timeout disable ON
Error Reporting
Advanced error reporting (AER) On
ECRC check Off
ECRC generation Off
ECRC forwarding Off
Track receive completion buffer overflow Off
Link Capabilities
Link port number 1
Data link layer active reporting Off
Surprise down reporting Off
Slot clock configuration On
MSI Capabilities
MSI messages requested 4
MSI-X Capabilities
Implement MSI-X Off
MSI-X Table size 0
MSI-X Table Offset 0x0
MSI-X Table BAR Indicator (BIR) 0
Pending Bit Array (PBA) Offset 0x0
PBA BAR Indicator 0
Slot Capabilities
Use Slot Power registers (Root Port only) Off
Slot power scale 0
Slot power limit 0
Slot number 0
Table 4.  Power Management Parameters – Intel® Cyclone® 10 GX Device
Parameter Value
Power Management
Endpoint L0s acceptable latency Maximum of 64 ns
Endpoint L1 acceptable latency Maximum of 1 us
PHY Characteristics
Gen2 transmit deemphasis 6dB

Intel® Quartus® Prime Settings

The .qar files in the reference design package has the recommended synthesis, Fitter, and timing analysis settings. These settings are optimized for the parameters chosen in this reference design.

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