R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 4/12/2024
Public
Document Table of Contents

2.7. Running the Design Example

Here are the test operations you can perform on the R-Tile Avalon® -ST for PCIe design examples:

Table 10.  Test Operations Supported by the R-Tile Avalon® -ST IP for PCIe Design Examples
Operations Required BAR Supported by R-Tile Avalon® -ST IP for PCIe Design Examples
PIO SR-IOV Performance
0: Link test - 100 writes and reads 0 Yes Yes No
1: Write memory space 0 Yes Yes No
2: Read memory space 0 Yes Yes No
3: Write configuration space N/A Yes No No
4: Read configuration space N/A Yes No No
5: Change BAR N/A Yes Yes No
6: Change device N/A Yes Yes No
7: Enable SR-IOV N/A No Yes No
8: Do a link test for every enabled virtual function belonging to the current device N/A No Yes No
9: Perform DMA for performance test N/A No No Yes
Note: When using the Agilex™ 7 I-Series FPGA Development Kit, set the PCIe REFCLK Select switch to select the clock from the PCIe Connector. For more details, refer to the Agilex™ 7 I-Series FPGA Development Kit User Guide.