AN 829: PCI Express* Avalon® -MM DMA Reference Design

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ID 683554
Date 6/11/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design x
1.1. Introduction 1.2. Working with the Reference Design 1.3. Understanding PCI Express Throughput 1.4. Document Revision History for AN 829: PCI Express* Avalon® -MM DMA Reference Design
1.1. Introduction x
1.1.1. DMA Reference Design Hardware and Software Requirements 1.1.2. Avalon® -MM DMA Bridge Module Descriptions
1.2. Working with the Reference Design x
1.2.1. Project Hierarchy 1.2.2. Parameter Settings for PCI Express Hard IP Variations 1.2.3. PCIe* Avalon® -MM DMA Reference Design Platform Designer Systems 1.2.4. DMA Procedure Steps 1.2.5. Setting Up the Hardware 1.2.6. Programming the Intel® Cyclone® 10 GX FPGA Oscillator 1.2.7. Installing the DMA Test Driver and Running the Linux DMA Software
1.3. Understanding PCI Express Throughput x
Protocol Overhead 1.3.1. Throughput for Posted Writes 1.3.2. Throughput for Reads 1.3.3. Throughput Differences for On-Chip and External Memory
1.3.1. Throughput for Posted Writes x
1.3.1.1. Specifying the Maximum Payload Size
1.3.2. Throughput for Reads x
1.3.2.1. Understanding Throughput Measurement
1. AN 829: PCI Express* Avalon® -MM DMA Reference Design

1.3. Understanding PCI Express Throughput

The throughput in a PCI Express system depends on the following factors:

  • Protocol overhead
  • Payload size
  • Completion latency
  • Flow control update latency
  • Devices forming the link

Protocol Overhead

Protocol overhead includes the following three components:

  • 128b/130b Encoding and Decoding—Gen3 links use 128b/130b encoding. This encoding adds two synchronization (sync) bits to each 128-bit data transfer. Consequently, the encoding and decoding overhead is very small at 1.56%. The effective data rate of a Gen3 x8 link is about 8 gigabytes per second (GBps).
  • Data Link Layer Packets (DLLPs) and Physical Layer Packets (PLPs)—An active link also transmits DLLPs and PLPs. The PLPs consist of SKP ordered sets which are 16-24 bytes. The DLLPs are two dwords. The DLLPs implement flow control and the ACK/NAK protocol.
  • TLP Packet Overhead—The overhead associated with a single TLP ranges from 5-7 dwords if the optional ECRC is not included. The overhead includes the following fields:
    • The Start and End Framing Symbols
    • The Sequence ID
    • A 3- or 4-dword TLP header
    • The Link Cyclic Redundancy Check (LCRC)
    • 0-1024 dwords of data payload
Figure 11. TLP Packet Format

Section Content
Throughput for Posted Writes
Throughput for Reads
Throughput Differences for On-Chip and External Memory

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