E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 4/29/2024
Public
Document Table of Contents

4.2.5. 10GE/25GE Design Examples Registers

Table 30.   E-Tile Hard IP for Ethernet Intel FPGA IP Hardware Design Examples Register Map

Word Offset

Register Category

0x000000 – 0x000FFF Ethernet MAC and PCS registers
0x001000 – 0x001FFF Packet Generator and Checker registers
0x002000 – 0x002FFF PTP monitoring registers
0x004000 – 0x005FFF Triple-Speed Ethernet registers
0x006000 – 0x006FFF Triple-Speed Ethernet traffic controller registers
0x010000 – 0x0107FF RS-FEC configuration registers
0x100000 – 0x1FFFFF Transceiver registers
Table 31.  Packet Client Registers You can customize the E-Tile Hard IP for Ethernet Intel FPGA IP hardware design example by programming the packet client registers.

Addr

Name

Bit

Description

HW Reset Value

Access

0x1000 PKT_CL_SCRATCH [31:0] Scratch register available for testing. N/A RW
0x1001 PKT_CL_CLNT [31:0] Four characters of IP block identification string CLNT. N/A RO
0x1008 Packet Size Configure [29:0] Specify the transmit packet size in bytes. These bits have dependencies to PKT_GEN_TX_CTRL register.
  • Bit[29:11]: Reserved.
  • Bit[10:0]: These bits specify the transmit packet size in bytes.
0x25800040 RW
0x1009 Packet Number Control [31:0] Specify the number of packets to transmit from the packet generator. 0xA RW
0x1010 PKT_GEN_TX_CTRL [7:0]
  • Bit [0]: Reserved.
  • Bit [1]: Packet generator disable bit. Set this bit to the value of 1 to turn off the packet generator, and reset it to the value of 0 to turn on the packet generator.
  • Bit [2]: Reserved.
  • Bit [3]: Has the value of 1 if the IP core is in MAC loopback mode; has the value of 0 if the packet client uses the packet generator.
  • Bit [5:4]:
    • 00: Reserved
    • 01: Fixed mode
    • 10: Reserved
  • Bit [6]: Set this bit to 1 to use 0x1009 register to turn off packet generator based on a fixed number of packets to transmit. Otherwise, bit[1] of PKT_GEN_TX_CTRL register is used to turn off the packet generator.
  • Bit [7]
    • 1: For transmission without gap in between packets.
    • 0: For transmission with random gap in between packets.
0x6 RW
0x1011 Destination address lower 32 bits [31:0] Destination address (lower 32 bits). 0x56780ADD RW
0x1012 Destination address upper 16 bits [15:0] Destination address (upper 16 bits). 0x1234 RW
0x1013 Source address lower 32 bits [31:0] Source address (lower 32 bits). 0x43210ADD RW
0x1014 Source address upper 16 bits [15:0] Source address (upper 16 bits). 0x8765 RW
Table 32.  1GE Packet Generator Registers You can customize the E-Tile Hard IP for Ethernet Intel FPGA IP hardware design example by programming the 1GE packet generator registers.

Address

Name

Bit

Description

HW Reset Value

Access

0x800 NUMPKTS [31:0] The total number of Ethernet packets that the traffic generator generates and transmits to the design components. 0x0 RW
0x804 RANDOMLENGTH [31:0]
Enables random packet length up to the value of the PKTLENGTH register.
  • 0x00: Fixed
  • 0x01: Random length
0x0 RW
0x808 RANDOMPAYLOAD [31:0]

Enables random contents of the payload.

  • 0x00: Incremental
  • 0x01: Random
0x0 RW
0x80C START [31:0] StartS the generation of the Ethernet traffic by writing 0x01 to this register. 0x0 RW
0x834 PKTLENGTH [31:0] When random-sized packets are enabled, this register specifies the maximum payload length. Otherwise, it specifies the length of the packet to be generated. 0x0 RW
Table 33.  1GE Traffic Monitor Registers You can customize the E-Tile Hard IP for Ethernet Intel FPGA IP hardware design example by programming the 1GE traffic monitor registers.

Address

Name

Bit

Description

HW Reset Value

Access

0x900 RXPKTCNT_EXPT [31:0] The total number of packets that the traffic monitor expects to receive. 0x0 RW
0x904 RXPKTCNT_GOOD [31:0]

The total number of good packets received by the traffic monitor.

0x0 RO
0x908 RXPKTCNT_BAD [31:0] The total number of packets received with CRC error. 0x0 RO
0x91C RXCTRL_STATUS [31:0]

Monitors the configuration and status register.

  • Bit [0]: Set to 1 to initialize all of the traffic monitor counters.
  • Bit [1]: Reserved.
  • Bit [2]: When set to 1, indicates that the traffic monitor has received the total number of expected packets. This bit is a read-only bit.
  • Bit [31:3]: Reserved.
0x0 RW
Table 34.  CPRI PHY Soft Configuration Register Space
Address Name Bit Description HW Reset Value Access
0x3000 cpri_rate_sel [3:0] eFIFO and deterministic latency use this register for 1G Ethernet speed.
  • Bit [3:0] = 0x1 for 1G
  • All other values are reserved.
Note: The TX/RX datapath must be reconfigured after change this register.
0xB RW
Note: In the 10G/25G Ethernet Design Example variant, the context CPRI PHY soft configuration register space does not refer to the CPRI PHY IP's register space.