E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 4/29/2024
Public
Document Table of Contents

2.1.5. Compiling and Configuring the Design Example in Hardware

To compile the hardware design example and configure it on your Stratix® 10 device, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/alt_ehip3.qpf.
  3. On the Processing menu, click Start Compilation.
  4. After successful compilation, a .sof file is available in <design_example_dir>/hardware_test_design/output_files directory. Follow these steps to program the hardware design example on the Stratix® 10 device:
    1. Connect Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit to the host computer.
    2. Launch the Clock Control application, which is part of the development kit, and set new frequencies for the design example. Below is the frequency setting in the Clock Control application:
      • Y1—Set to the PHY Reference Frequency specified in the PMA adaptation setting of your IP core variation.

        For 10GE/25GE variant, select 10GE/25GE tab and locate the PMA Options 10GE/25GE setting.

        For 100GE variant, select 100GE tab and locate the PMA Options 100GE setting.

      • U3, OUT3—100 MHz
    3. On the Tools menu, click Programmer.
    4. In the Programmer, click Hardware Setup.
    5. Select a programming device.
    6. Select and add the Stratix 10 E-Tile TX Transceiver Signal Integrity Development Kit to which your Quartus® Prime Pro Edition session can connect.
    7. Ensure that Mode is set to JTAG.
    8. Select the Stratix® 10 device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
    9. In the row with your .sof, check the box for the .sof.
    10. Check the box in the Program/Configure column.
    11. Click Start.