E-Tile Hard IP Stratix® 10 Design Examples User Guide: Ethernet, CPRI PHY, and Dynamic Reconfiguration

ID 683578
Date 4/29/2024
Public
Document Table of Contents

3.2.4. Interface Signals

Table 20.  Design Example Interface Signals
Signal Direction Description
ref_clk100MHz Input Input clock for CSR access on all the AV-MM interfaces. Drive at 100 MHz.
ref_clk156MHz Input Reference clock for channel PLL. Drive at 156.25 MHz.
i_clk_ref Input Transceiver reference clock. Drive at
  • 153.6 MHz for CPRI line rates 2.4/3/4.9/6.1/9.8 Gbps.
  • 184.32 MHz for CPRI line rates 10.1, 12.1, and 24.3 Gbps with and without RS-FEC.
i_rx_serial[n] Input Transceiver PHY input serial data.
o_tx_serial[n] Output Transceiver PHY output serial data.