E-Tile Hard IP for Ethernet Release Notes

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ID 683582
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. E-Tile Hard IP for Ethernet Release Notes 2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes 3. E-Tile Ethernet IP for Intel Agilex® 7 FPGA Release Notes 4. E-tile Hard IP User Guide Archives
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes x
2.1. E-Tile Hard IP for Ethernet Intel® FPGA IP v24.0.0 2.2. E-Tile Hard IP for Ethernet Intel® FPGA IP v23.0.0 2.3. E-Tile Hard IP for Ethernet Intel® FPGA IP v22.0.0 2.4. E-Tile Hard IP for Ethernet Intel® FPGA IP v21.0.0 2.5. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.3.0 2.6. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.1 2.7. E-Tile Hard IP for Ethernet Intel® FPGA IP v20.2.0 2.8. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.4.0 2.9. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.3.0 2.10. E-Tile Hard IP for Ethernet Intel® FPGA IP v19.2 2.11. E-tile Hard IP for Ethernet Intel® FPGA IP v19.1 2.12. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1.1 2.13. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.1 2.14. E-Tile Hard IP for Ethernet Intel® FPGA IP v18.0
3. E-Tile Ethernet IP for Intel Agilex® 7 FPGA Release Notes x
3.1. E-Tile Ethernet IP for Intel Agilex FPGA v24.0.1 3.2. E-Tile Ethernet IP for Intel Agilex FPGA v23.0.0 3.3. E-Tile Ethernet IP for Intel Agilex FPGA v22.0.0 3.4. E-Tile Ethernet IP for Intel Agilex FPGA v21.0.0 3.5. E-Tile Ethernet IP for Intel Agilex FPGA v20.2.0 3.6. E-Tile Ethernet IP for Intel Agilex FPGA v20.1.1 3.7. E-Tile Ethernet IP for Intel Agilex FPGA v19.4.0 3.8. E-Tile Ethernet IP for Intel Agilex FPGA v19.3.0
1. E-Tile Hard IP for Ethernet Release Notes
2. E-Tile Hard IP for Ethernet Intel® FPGA IP Release Notes
3. E-Tile Ethernet IP for Intel Agilex® 7 FPGA Release Notes
4. E-tile Hard IP User Guide Archives

3.2. E-Tile Ethernet IP for Intel Agilex FPGA v23.0.0

Table 18.  v23.0.0 2023.01.31
Intel® Quartus® Prime Version Description Impact
22.4 Corrected the E-Tile Ethernet IP generation error when adding support for the Intel Agilex® 7 device in Quartus. —
Updated signal properties for platform design. Changed the display signal property from reset to reset_n.
Fixed tri-state buffer/node warning. —
Enabled Passing PMA Adaption parameters to native PHY in 100G PTP FEC mode. When enabled, IP parameters are passed to PMA in 100G PTP FEC mode.
Fixed critical warnings for 100G E-Tile Dynamic Reconfiguration Design Example. —
When Enable Native PHY Debug Master Endpoint(NPDME) parameter is disabled, access to the Native PHY PMA capability registers is enabled. —
Level Two Title