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1. Datasheet
2. Intel Stratix 10 LL 40GbE IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Intel® Stratix® 10 Low Latency 40GbE IP Core User Guide Archives
11. Differences Between Intel Stratix 10 LL 40GbE IP Core and Low Latency 40GbE IP Core That Targets an Arria 10 Device
12. Document Revision History for Low Latency 40-Gbps Ethernet Intel Stratix 10 IP Core
3.1. Installing and Licensing Intel® FPGA IP Cores
3.2. Specifying the Intel Stratix 10 LL 40GbE IP Core Parameters and Options
3.3. Simulating the IP Core
3.4. Generated File Structure
3.5. Integrating Your IP Core in Your Design
3.6. Intel Stratix 10 LL 40GbE IP Core Testbench
3.7. Compiling the Full Design and Programming the FPGA
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9.1. Features
The Ethernet Toolkit offers the following features when used with hardware design that has standalone Ethernet IP as well as with an Intel® Quartus® Prime generated Ethernet IP design example:
- Verifies the status of the Ethernet link.
- Reads and writes to status and configuration registers of the IP.
- Displays the values of TX/RX status and statistics registers.
- Ability to assert and deassert IP resets.
- Verifies the IPs error correction capability.
The Ethernet Toolkit also offers some additional features when used with an Intel® Quartus® Prime generated Ethernet IP design example:
- Provides access to the example design packet generator.
- Execute testing procedures to verify the functionality of Ethernet IPs.
- Enable and disable MAC loopback.
- Set source and destination MAC addresses.
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