| 2021.02.09 |
20.4 |
Updated the description for temperature sensor error codes 0x80000001 and 0x80000005. |
| 2020.10.19 |
20.3 |
- Added related information links to voltage and temperature sensor specifications.
- Updated the Internal Temperature Sensor topic to improve accuracy.
- Added guidelines topic about calibrating the external temperature sensing chip.
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| 2019.10.09 |
19.3 |
- Updated the note about transceiver tile availability to provide an example of the CH0 and CH1 temperature sensor channels locations for the Intel® Stratix® 10 GX 400, TX 400, and SX 400 devices.
- Added a topic listing the temperature sensor error codes.
- Updated the following IP names:
- From "Voltage Sensor Intel® Stratix® 10 FPGA IP" to "Voltage Sensor Intel® FPGA IP".
- From "Temperature Sensor Intel® Stratix® 10 FPGA IP" to "Temperature Sensor Intel® FPGA IP".
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| 2019.07.09 |
19.2 |
- Added a guideline topic about selecting a temperature sensing chip to interface with the Intel® Stratix® 10 external TSD.
- Updated the guideline topic about using external temperature sensors.
|
| 2019.05.17 |
19.1 |
Added a note regarding IP core instantiation guidelines in the topics about sampling the voltage sensor and reading the internal temperature sensor. |
| 2019.05.13 |
19.1 |
- Updated the topic about the voltage sensor to clarify that although the ADC supports up to 1.24 V input voltage, the Voltage Sensor IP core can measure the 1.8 V internal power supplies.
- Corrected the channel numbers of the internal TSDs in the HBM2 blocks.
- Added a note to clarify that you cannot simulate the Voltage Sensor and Temperature Sensor IP cores. Instead, validate the IP cores through hardware evaluation.
|
| 2018.11.05 |
18.1 |
- Updated the topic about the Intel® Stratix® 10 ADC architecture and features to improve clarity.
- Removed external VREF support for the Intel® Stratix® 10 voltage sensor:
- Removed the VREFP_ADC and VREFN_ADC pins from the Intel® Stratix® 10 voltage sensor diagram.
- Removed the guideline topic about connecting external voltage reference to the Intel® Stratix® 10 ADC voltage reference pins.
- Updated the Intel® Stratix® 10 voltage sensor diagram:
- Updated communication between the blocks labeled "SDM" and "Voltage Sensor IP Core" to bidirectional.
- Updated the legend for the shared pin to clarify that the pin is shared with the device, not the GPIO.
- Updated the topic about the Intel® Stratix® 10 voltage sensor:
- Specified that the ADC samples the voltage at regular intervals.
- Updated the maximum value of the external analog signal from 1.25 V to 1.24 V.
- Updated the topic about the Intel® Stratix® 10 internal temperature sensor to specify that the ADC samples the voltage at regular intervals.
- Updated the topic that lists the temperature sensor channels and locations to clarify that you specify the internal TSD channels to sample through the cmd_data signal.
- Updated the ADC implementation guides topic to clarify that you only need to instantiate one instance of the IP core and interact with it using its digital signal interface.
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| 2018.07.19 |
18.0 |
- Removed the word "speed" from the note about the clock source to the Temperature Sensor IP core in the topic about the internal temperature sensor. You can use any clock source between 10 MHz to 100 MHz.
- Updated the steps for sampling the voltage sensor and reading the internal temperature sensor. The updated steps clarify that you must keep the Voltage Sensor or Temperature Sensor IP core in reset mode during device initialization until the device enters user mode.
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| 2018.05.07 |
18.0 |
- Updated the IP names from "Intel® FPGA S10 Voltage Sensor" and "Intel® FPGA S10 Temperature Sensor" to "Voltage Sensor Intel® Stratix® 10 FPGA IP" and "Temperature Sensor Intel® Stratix® 10 FPGA IP".
- Added information about transceiver tile's internal and external TSD availability when the tile is powered down.
- Added support for temperature sensors in the HBM2 stacks.
- Updated the diagram and description to identify the location and availability of the TSDs by using transceiver bank numbers instead of 3 V I/O bank numbers.
- Updated the table listing the internal TSD channels and external TSD pins to improve clarity.
- Updated the topics describing the steps to access the voltage and temperature sensor readouts:
- Added steps to perform during device initialization.
- Removed mentions of "continuous sampling" and specified that you must assert cmd_valid only for one to three clock cycles.
- Updated the introduction for the Intel® Stratix® 10 ADC IP core reference section.
- Updated the frequency supported by the clk signal of the ADC IP cores from 250 MHz to a range of 10 MHz to 100 MHz.
- Added the rsp_data response value that indicates invalid data.
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