Nios® V Processor Reference Manual

Download PDF
ID 683632
Date 10/31/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/m Processor 3. Nios V Processor Reference Manual Archives 4. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Intel® Quartus® Prime Software Support
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Control and Status Registers 2.3.5. Exception Controller 2.3.6. Interrupt Controller 2.3.7. Memory and I/O Organization 2.3.8. RISC-V based Debug Module
2.3.6. Interrupt Controller x
2.3.6.1. Timer and Software Interrupt Module
2.3.7. Memory and I/O Organization x
2.3.7.1. Instruction and Data Buses
2.3.7.1. Instruction and Data Buses x
2.3.7.1.1. Instruction Manager Port 2.3.7.1.2. Data Manager Port 2.3.7.1.3. Address Map
2.3.8. RISC-V based Debug Module x
2.3.8.1. Debug Mode 2.3.8.2. Halt from Debug Module 2.3.8.3. Trigger 2.3.8.4. Abstract Commands in Debug Mode 2.3.8.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. Overview
2. Nios® V/m Processor
3. Nios V Processor Reference Manual Archives
4. Document Revision History for the Nios® V Processor Reference Manual

2.1. Processor Performance Benchmarks

Table 2.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Pro Edition
FPGA Used fMAX (MHz) Logic Size (ALM) Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® 10 274.05 1350 0.572 0.402
Intel® Arria® 10 304.63 1382
Intel® Stratix® 10 373.55 1570
Intel® Agilex™ 560.93 1523
Table 3.   Nios® V/m Processor Performance Benchmarks in Intel FPGA Devices for Intel® Quartus® Prime Standard Edition
FPGA Used fMAX (MHz) Logic Size Architecture Performance
DMIPS/MHz Ratio CoreMark/MHz Ratio
Intel® Cyclone® IV E 139.63 2958 (LE) 0.572 0.402
Intel® Cyclone® V 162.1 1302.9 (ALM)
Intel® Arria® V 198.65 1308.5 (ALM)
Intel® Arria® V GZ 266.52 1263.9 (ALM)
Intel® Stratix® V 329.38 1280.3 (ALM)
Intel® Cyclone® 10 LP 134.44 2946 (LE)
Intel® Arria® 10 325.41 1283.1 (ALM)
Intel® MAX® 10 105.89 2997 (LE)
Table 4.  Benchmark Parameters
Parameter Settings/Description
Intel® Quartus® Prime seed Maximum performance result are based on 10 seed sweep from Intel® Quartus® Prime Pro Edition software version 22.3.
Device speed grade Fastest speed grade from each Intel FPGA device family.
Defined peripherals
  • Nios® V/m processor core
  • 4 KB on-chip memory for the instruction bus
  • 4 KB on-chip memory for data bus
  • Avalon® Memory-Mapped Pipeline Bridge
Toolchain Version
  • riscv32-unknown-elf-gcc (GCC) version 11.2.0
  • CMake Version: 3.23.2
Compiler configuration
  • Compiler flags: -03
  • Assembler options: -Wa -gdwarf2
  • Compile options: -Wall -Wformat-security -march=rv32ia -mabi=ilp32
Intel uses the same Intel® Quartus® Prime design example for maximum performance benchmark(fMAX) and logic size benchmarks. However, the compiler settings are different for each benchmarks:
  • fMAX benchmark: superior_performance_optimized_placement_effort
  • Logic size benchmark: area_aggressive
Note: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.
Level Two Title