10. Document Revision History for the 25G Ethernet Intel® Arria® 10...

25G Ethernet Intel® Arria® 10 FPGA IP User Guide

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Date 3/29/2021

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10. Document Revision History for the 25G Ethernet Intel® Arria® 10 FPGA IP User Guide

Document Version	Intel® Quartus® Prime Version	IP Version	Changes
2021.03.29	21.1	19.4.0	Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface: `tx_etstamp_ins_ctrl_residence_time_calc_format` `tx_egress_timestamp_64b_data[63:0]` `tx_egress_timestamp_96b_fingerprint[(W–1):0]` `tx_egress_timestamp_64b_fingerprint[(W–1):0]`
2020.10.12	20.3	19.4.0	Updated the description in the About the 25G Ethernet Intel FPGA IP section. Updated the description in the 25G Ethernet Intel FPGA IP Supported Features section.25G Ethernet Intel FPGA IP Supported Features Added a note to the Length Checking section to state that the MAC has a counter limit of 0xFFFF starting from Intel® Quartus® Prime Pro Edition software version 20.3 onward. Made minor editorial updates throughout the document.
2020.06.22	19.4	19.4.0	Updated the Length/Type Field Processing section. Update the descriptions to the following signals in Table: Avalon® Streaming TX Datapath: `l1_tx_data[63:0]` `l1_tx_valid` `l1_tx_ready` Removed Figure: Client to 25G Ethernet Intel FPGA IP MAC Avalon Streaming Interface. Added the following Figures: Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (1 of 2) Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 0 (2 of 2) Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (1 of 2) Client to 25G Ethernet Intel FPGA IP MAC Avalon® Streaming Interface when Ready Latency is 3 (2 of 2)
2020.04.13	19.4	19.4.0	Updated the Simulating the IP Core section. Updated the Length Checking section. Updated Table: Avalon® Streaming RX Datapath to update the description for `l1_rx_error[5:0]`. Updated Table: Receive Side Statistics Registers to update the descriptions for `CNTR_RX_1519toMAXB_HI`, `CNTR_RX_OVERSIZE_LO`, and `CNTR_RX_OVERSIZE_HI`. Updated the description and reset value for `RXMAC_CONTROL` and description for `LINK_FAULT` in Table: RX MAC Registers.
2020.02.20	19.4	19.4.0	Updated the description for frame monitoring and statistics in the 25G Ethernet Intel FPGA IP Core Supported Features section. Updated the Debugging the Link section.
2019.12.16	19.4	19.4.0	Updated the description in the About the 25G Ethernet Intel FPGA IP Core section. Updated Table: IP Core FPGA Resource Utilization for 25G Ethernet Intel FPGA IP Core for Intel® Arria® 10 Devices. Updated the description in the PTP Transmit Functionality section. Updated the descriptions for the following signals in Table: Signals of the 1588 Precision Time Protocol Interface: `tx_etstamp_ins_ctrl_offset_timestamp[15:0]` `tx_etstamp_ins_ctrl_offset_correction_field[15:0]` `tx_etstamp_ins_ctrl_offset_checksum_field[15:0]` `tx_etstamp_ins_ctrl_offset_checksum_correction[15:0]` Added `rx_am_lock` to Table: Miscellaneous Status and Debug Signals. Updated the description and reset value for `RXMAC_CONTROL` in Table: RX MAC Registers. Updated the description of the Avalon® Memory-Mapped Management Interface section. Updated the Statistics Registers section. Renamed Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME). Updated for latest Intel® branding standards.
2018.10.23	17.0	17.0	Updated Table: PHY Registers: Added bit[1] description for `RX_PCS_FULLY_ALIGNED_S`. Updated the descriptions for `KHZ_REF`, `KHZ_RX`, and `KHZ_TX`. Made minor editorial updates to the document.
2018.07.17	17.0	17.0	Renamed the document as 25G Ethernet Intel Arria 10 FPGA IP User Guide. Renamed "25G Ethernet" IP core to "25G Ethernet Intel FPGA IP" as per Intel rebranding. Updated Table: TX 1588 PTP Registers to correct the HW reset value of the `TX_PTP_CLK_Period` register to 0x28F5C. Updated Table: RX 1588 PTP Registers to correct the HW reset value of the `RX_PTP_CLK_Period` register to 0x28F5C. Updated for latest Intel branding standards.

Date	Quartus Prime Version	Changes
2017.11.07	17.0	Added link to KDB Answer that provides workaround for potential jitter on Intel® Arria® 10 devices due to cascading ATX PLLs in the IP core. Refer to Handling Potential Jitter in Intel Arria 10 Devices .
2017.08.28	17.0	Updated for new Quartus Prime software v17.0 release Updated instructions to generate the IP core. Refer to Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options Updated IP Cores Generated Files figure. Refer to Generated File Structure. Updated information about specification compliance. The IP core now complies with Draft 1.6 of the 25G & 50G Ethernet Specification from the 25 Gigabit Ethernet Consortium, and the IEEE 802.3by 25Gb Ethernet specification is no longer a draft. Refer to About the 25G Ethernet Intel FPGA IP and 25G Ethernet Intel FPGA IP Supported Features. Added shadow feature for reading statistics registers. Replaced the `CLEAR_TX_STATS` and `CLEAR_RX_STATS` registers with new `CNTR_TX_CONFIG` and `CNTR_RX_CONFIG` registers at offsets 0x845 and 0x945. Added new `CNTR_TX_STATUS` and `CNTR_RX_STATUS` registers at offsets 0x846 and 0x946, respectively . Refer to Statistics Registers. Removed statements that parameter editor fails to enforce certain incompatible parameter constraints. The IP core parameter editor no longer allows you to select unsupported parameter value combinations. Refer to 25G Ethernet Intel FPGA IP Parameters. Removed Vendor ID from Release Information. Clarified that the IP core `clk_ref` input signal and the ATX PLL reference clock input signal must be driven by the same clock. Refer to Adding the Transceiver PLL. Clarified that the design example includes SDC files that you can modify for your own design. Refer to Compiling the Full Design and Programming the FPGA. Clarified that the IP core does not support VHDL models. Refer to Specifying the 25G Ethernet Intel FPGA IP Core Parameters and Options and Generated File Structure. Clarified that the TX statistics counters do not count the errors you generate by asserting the `l1_tx_error` signal. Refer to TX MAC Interface to User Logic and TX Statistics Registers. Clarified that both read and write accesses to undefined registers or register fields, including accesses to registers and register fields not defined in the current IP core variation, return unspecified results. Refer to Control, Status, and Statistics Register Descriptions. Removed the section "Creating a Signal Tap II Debug File to Match Your Design Hierarchy" from the Debugging chapter. The files cited (build_stp.tcl) do not exist in the file hierarchy generated by the Intel® Quartus® Prime Standard Edition v17.0 software. Reworded the definitions of the TX flow control/PFC registers at offsets 0x606 and 0x641 for clarity. The register functionality has not changed. Refer to Pause/PFC Flow Control Registers. Updated flow control register descriptions to use the variable FCQN as it is defined in TX MAC Interface to User Logic: the number of flow control queues in the IP core. Refer to Pause/PFC Flow Control Registers. Updated `REV_ID` register values in Pause/PFC Flow Control Registers, 1588 PTP Registers,TX Reed-Solomon FEC Registers and RX Reed-Solomon FEC Registers. Added clarification that non-character bytes in `NAME` registers are not printable, in register sections that previously indicated only the value zero for these bytes. Refer to PHY Registers and Pause/PFC Flow Control Registers. Mentioned that the IP core does not correctly flag received non-zero 4-bit ordered set types as erroneous. Refer to IP Core Malformed Packet Handling and Link Fault Signaling Interface. Added reference to Intel FPGA Answer that explains the requirement for certain additions to .sdc file. Refer to Compiling the Full Design and Programming the FPGA. Reorganized Features list for reading clarity. Refer to 25G Ethernet Intel FPGA IP Supported Features. Fixed assorted typos and minor errors.
2016.10.31	16.1	Initial release.