ASMI Parallel II Intel® FPGA IP User Guide

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ID 683669
Date 10/09/2023
Public
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ASMI Parallel II Intel® FPGA IP User Guide
ASMI Parallel II Intel® FPGA IP User Guide x
Release Information Ports Parameters Register Map Operations ASMI Parallel II Intel® FPGA IP Use Case Examples ASMI Parallel II Intel® FPGA IP User Guide Archives Document Revision History for the ASMI Parallel II Intel® FPGA IP User Guide
Operations x
Control Status Register Operations Memory Operations
ASMI Parallel II Intel® FPGA IP Use Case Examples x
Example 1: Read the Silicon ID of the Configuration Devices Example 2: Read and Write One Word of Data at Address H'40000000 Example 3: Erase Sector 64 Example 4: Perform Sector Protect at Sectors (0 to 127) Example 5: Read and Clear Flag Status Register Example 6: Read and Write nvcr
ASMI Parallel II Intel® FPGA IP User Guide

Memory Operations

The ASMI Parallel II Intel® FPGA IP memory interface supports bursting and direct flash memory access. During the direct flash memory access, the IP performs the following steps to allow you to perform any direct read or write operation:

  • Write enable for the write operation
  • Check flag status register to make sure the operation has been completed at the flash
  • Release the waitrequest signal when the operation is completed

Memory operations are similar to the Avalon® memory-mapped interface operations. You must set the correct value at the address bus, write data if it is a write transaction, drive the burst count value to 1 for single transaction or your desired burst count value, and trigger the write or read signal.

Figure 4. 8-Word Write Burst Waveform Example
Figure 5. 8-Word Reading Burst Waveform Example
Figure 6. 1-Byte Write byteenable = 4’b0001 Waveform Example
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