Low Latency 50G Ethernet Intel® FPGA IP User Guide: Stratix® 10 Devices

ID 683675
Date 4/09/2024
Public
Document Table of Contents

6.6.25. Local Transceiver TX EQ 1 Settings for Lane 1

Provides the following Local TX EQ 1 Settings for Lane 1
  • Local TX EQ VOD Setting for Lane 1
  • Local TX EQ Post-Tap Setting for Lane 1
  • Local TX EQ Pre-Tap Setting for Lane 1

Offset: 0xE2

Access: RO

Local Transceiver TX EQ 1 Settings for Lane 1 Fields

Bit Name Description Access Reset
20:16 lt_pretap_setting_ln1 Local TX EQ Pre-tap Setting for Lane 1

This register returns the most recent Pre-tap setting that was written to the local transceiver.

RO 0x0
13:8 lt_posttap_setting_ln1 Local TX EQ Post-tap Setting for Lane 1

This register returns the most recent Post-tap setting that was written to the local transceiver

RO 0x0
4:0 lt_vod_setting_ln1 Local TX EQ VOD Setting for Lane 1

This register returns the most recent VOD setting that was written to the local transceiver

RO 0x0