AN 837: Design Guidelines for HDMI Intel FPGA IP

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ID 683677
Date 1/28/2019
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for HDMI Intel® FPGA IP 2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP
1. Design Guidelines for HDMI Intel® FPGA IP x
1.1. HDMI Intel® FPGA IP Design Guidelines 1.2. HDMI Intel® FPGA IP Board Design Tips 1.3. Schematic Diagrams 1.4. Hot-Plug Detect (HPD) 1.5. HDMI Intel® FPGA IP Display Data Channel (DDC)
1. Design Guidelines for HDMI Intel® FPGA IP
2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP

1.2. HDMI Intel® FPGA IP Board Design Tips

When you are designing your HDMI Intel® FPGA IP system, consider the following board design tips.
  • Use no more than two vias per trace and avoid via stubs
  • Match the differential pair impedance to the impedance of the connector and cable assembly (100 ohm ±10%)
  • Minimize inter-pair and intra-pair skew to meet the TMDS signal skew requirement
  • Avoid routing a differential pair over a gap in the underneath plane
  • Use standard high speed PCB design practices
  • Use level shifters to meet electrical compliance at both TX and RX
  • Use robust cables, such as Cat2 cable for HDMI 2.0
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